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Part 1

Computer Systems
Hardware
(Book No. 1 Chapter 2)

HARDWARE
2.1 Information element
2.2 Processor architecture
2.3 Memory architecture
2.4 Auxiliary storage devices
2.5 Input/output architecture and devices





Introduction
Functions of hardware in a computer
can be divided into five main units
Five Main Units in Computing
Central Processing Unit
3. Arithmetic Unit
Performs calculation and decision on stored data based on
instructions of the program.
4. Control Unit
Controls all other units
Peripheral Units
1. Input Unit
Inputs data and programs for processing.
5. Output Unit
Output results in a format understood by humans.
2. Storage Unit
Stores the input data and program
Input Unit
Main Storage
Unit
Output Unit
Arithmetic
Unit
Control Unit
Processor (CPU)
Data Flow
Control Flow
5 main units of computers
2.1 Information Element
Integrated Circuit
Uses
Levels of integration
Semiconductor Memory
Different types of RAM
Different types of ROM
IC
Sometimes called a chip or microchip, is a
semiconductor wafer on which thousands or
millions of tiny resistors, capacitors, and
transistors are fabricated
An IC can function as an amplifier,
oscillator, timer, counter, computer
memory, or microprocessor

Integrated Circuit
Bipolar IC
Speed and power requirement as well as costs are high. Used as a
logic element.
In digital transmission, an electrical line signalling method where
the mark value alternates between positive and negative polarities.
Used in logical operations
CMOS (Complementary Metal Oxide Semiconductor) IC
Speed and power requirement as well as costs are low. Used as
storage element.
Used in data and instruction storage
IC Classification
IC Integration Level
SSI (Small Scale Integration) 10
1
10
2
MSI (Medium Scale Integration) 10
2
10
3
LSI (Large Scale Integration) 10
3
10
4
VLSI (Very Large Scale Integration) > 10
5
Transistors Per IC
Fujitsu Integrated Circuits
86903-33
Full die shot of the Fujitsu 86903-33 showing the
complete pad ring using oblique illumination with blue,
red, and yellow gels.

Sun Microsystems Integrated Circuits
UltraSPARC

Full die shot of the Sun Microsystems UltraSPARC
microprocessor showing the complete pad ring using
oblique illumination with red, blue, and yellow gels.
Intel Integrated Circuits
i4004
Full die shot of the Intel i4004 microprocessor showing the
complete pad with chip identifier, Intel logo, and bus
connections using oblique illumination with blue, red, and
yellow gels.

AMD Dual Core Architecture
Processor Architecture
Processor Structure
Control Unit
Arithmetic Unit (ALU)

Processor Operation Principles
Instruction readout and decoding
Instruction execution
Processor Structure
The CPU is the backbone of the computer,
often compared to the human brain.
It consists of the control unit and the
arithmetic unit.


Processor Structure
Control Unit
Controls all operations of the computer
Retrieves instruction stored in main storage unit
Decodes retrieved instruction using the instruction
decoder
Executes and transmits instructions to each unit.

The control unit controls each unit and implements the function
of each of the units as a computer system. The system by which
instructions are executed in this way, sequentially, is called
sequential control system, which is based on the concept of
John Von Neumann.
Von Neumann Architecture
Four main parts
Arithmetic unit
Control unit
Memory
Input/Output devices
Instructions are
stored and executed
sequentially

Sequential control system
Processor Structure
Arithmetic Unit or officially the Arithmetic
Logic Unit (ALU)
Performs calculations, comparison, branch and
other processes.
Depending on the representation method of data
assigned subject to operations, ALU has functions
performing fixed point operation, floating point
operation and decimal
A number representation consisting of a mantissa, M, an exponent, E, and an
(assumed) radix (or "base") . The number represented is M*R^E where R is
the radix - usually ten but sometimes 2.

ALU
Processor operation principles
Instruction readout and decoding
Instruction and instruction format
Instruction readout
Instruction decoding
Instruction execution
Storing retrieved data
Instruction execution
Processing subsequent to the instruction execution
Flow of instruction from decoding to execution and
hardware structure
Various registers

Processor Insight
Instruction 1
Instruction 2
Read/write controller
A
d
d
r
e
s
s

d
e
c
o
d
e
r

M
a
i
n

S
t
o
r
a
g
e

U
n
i
t

ALU
GR 0
GR 1
GR 2
GR n
Instruction
decoder
Operation Address
+1
Control unit Arithmetic unit
PC
IR
Control bus
Address bus
Data bus
Processor
Base Address
Flag
PSW
Index
Complement
Executing Program
Processor's four operating stages
Fetch a program's instructions and any
needed data into the processor
Decode determines the purpose of the
instruction and passes it to the appropriate
hardware element
Executing Program
Processor's four operating stages
Execute carries out the instruction
Retire takes the results of the execution stage
and places them into other processor registers
or the computer's main memory
Clock
An important part of a microprocessor is its
built-in clock, which determines the
maximum speed at which other units can
operate and helps synchronize related
operations
2 GHz 2 billion clock cycles per second
Silicon Structure
Fetch Logic
Decode/dispatch
L2 cache
L1 cache
Vector
Processing
Unit
Floating
Point Unit
Arithmetic
Logic Unit
Load /
Store Unit
Retire and write-back logic
Memory
Management
Unit
Branch
Processing
Unit
FETCH
DECODE
EXECUTE
RETIRE
Processor operation principles
Instruction readout and decoding
Data and program retrieved from the main
storage unit are transferred to the processor
through the data bus
This data is temporarily stored in the general-
purpose register
The instruction part is transferred to the
instruction register
Processor operation principles
Instruction readout and decoding
Instruction and instruction format
Instruction
A program is a set of instructions in the binary system called the machine
language instructions
A program written in any human language is converted to machine
language in order to be decoded and executed
Parts of the machine language
Instruction indicates instructions and operations
Address specifies the address and register of main storage unit subject to
processing
Processor operation principles
Instruction readout and format
Instruction format
Zero-address format
Uses a dedicated register called a stack pointer
Currently, not used
Stack pointer is the register that stores the address to be
returned to (return address) after completion
Instruction e.g. HALT
Processor operation principles
Instruction readout and format
Single-address format
Performs operations between the content of the main storage unit
specified in the address and the accumulator data
The accumulator stores operation values and operation results. There
are cases where general purpose registers are also used as accumulator
Two-address format
Specifies two addresses and uses the address data specified on the main
storage unit.
Three-address format
Specifies two addresses to be used for the operation, and the address
where the operation result is to be stored

Instruction Address e.g. INC GR1
Instruction Address Address e.g. MOV GR1, X
Instruction Address Address Address e.g. MUL GR3, GR2, GR1
Processor operation principles
Instruction Readout
Processor operation principles
Instruction Decoding
Content of instruction part of instruction
register is transferred to a decoder.
Decoder decodes the instruction and sends
signals for the execution of the operation to
each unit
Content of the address part is transferred to
the address bus
Processor operation principles
Instruction Decoding
Processor operation principles
Instruction Decoding
Processor operation principles
Instruction Execution
Once the instruction content and address of
the data are obtained, the instruction is
executed.
Processor operation principles
Instruction Execution
Storing retrieved data
If, as a result of decoding the instruction part and the address
part using the instruction decoder, the instruction is found to say
"Retrieve and transfer to the processor the contents of address
100 of the main storage unit," a place to store the retrieved
contents will be needed.
Therefore, a general-purpose register is set in the arithmetic unit
of the processor in order to store the retrieved data.
In this example, it is assumed that there are five registers, and,
for convenience, the numbers 0 to 4 will be assigned to them.
Then, using the initials of each of the general-purpose registers,
they will be represented as GR0, GR1, GR2, GR3 and GR4.
Processor operation principles
Instruction Execution
General-purpose registers
Processor operation principles
Instruction Execution
Contents of address 100 of the main storage unit (RAM)
passes through the data bus to be stored in general-purpose
register GR1
Processor operation principles
Instruction Execution
If, as a result of decoding the instruction, it is found to say
Add the contents of address 100 of RAM to the GR1
contents and store result in GR1
The unit that performs this kind of addition and subtraction
of numeric values is the ALU (Arithmetic and Logic Unit)
Fixed point operation mechanism to perform operations of integer
data (for scientific and engineering calculations)
Floating point operation mechanism to perform operations of floating
point data (for scientific and engineering calculations)
Decimal operation mechanism to perform operations of binary-coded
decimals in packet format (For commercial data processing)
Logical operations, logical sums, bit shifts
Processor operation principles
Instruction Execution
Storage of process result
Processor operation principles
Instruction Execution
Hardware structure
Processor operation principles
Registers
Types of registers
Program counter
Accumulator
Index register
Base address register
PSW (Program Status Word)
Flag register
Complement register
Register
Program Counter (PC)
A specialized register within the processor
When computer boots up, the content of the program counter is
immediately read and the address of the main storage unit to be
accessed is verified.
Load instruction A stored in address 101 of the RAM into the
processor

Register
Accumulator
Used to exclusively store operation results and values
There are cases where the general-purpose register is
used as a substitute for the accumulator
Accumulator mode: When the accumulator is used.
General purpose mode: When a general purpose register is used
as a substitute for the accumulator
Register
Index Register
Performs address modification
Changes address part of the instruction when an address in
the main storage unit is specified.
Register
Base register
Stores the program top address
Register
Flag register
Stores information related to operation result to
the existence of carry, overflow, etc
Register
Program Status Word (PSW)
The program counter, flag register and other information are
registered in the PSW.
If an event interrupts the program in the processor, the program
execution can be resumed using the PSW information
Register
Complement Register
Generates integer complements in order to perform
operations in the addition circuit
Address specification mode
Address part of instruction specifies main storage unit
address and the register subject to be processed
This address is not used during instruction execution.
The actual address is specified after performing
calculations between the specified register and the
addresses
This operation is called address modification
Actual address obtained is called the effective address



Address specification mode

Immediate specification
Direct address specification
Index address specification
Register address specification
Base address specification
Relative address specification
Indirect address specification
Immediate Specification
Data is contained in the address part, can
be executed immediately

Direct address specification
Address of data is contained in the address part
Index address specification
The address part is divided into the section that specifies the number of the
index register and the constant section, and the effective address is the
result of the following addition:
(Content of the register content specified with the register number) + (Address
constant)
Register Address Specification
Register number stored in address part
Address is stored in register of that number

Base address specification
The program starting address is stored in the base register
The result of the addition of the address in the base register
and the address constant becomes the effective address
Relative address specification
Result of the address of instruction being
executed and the address of the address part
become the effective address
Indirect address specification
Address of data is contained in the address
specified in the address part
May be performed on two or three levels
Processor operation principles
Instruction Set
When user inputs request, the software interacts with the hardware to
process the instructions built into the computer. This group of
instruction is called the instruction set
Depending on the computer, the types and number of instructions
differ
Computer software packages with identical instruction sets are
basically compatible
OS/2 Warp (Win OS/2 packaged)
Execution control of the instruction
Repetition of readout of instruction from main storage unit
Decoding and execution of instruction by control unit
* Instruction readout (I-cycle or Fetch cycle)
* Instruction execution (E-cycle)
I-Cycle and E-Cycle
Speed performance enhancement in
Processor
Machine Cycle
I-Cycle
E-Cycle
I-Cycle
E-Cycle
Sequential
processing
Pipeline
processing
Instruction Set
Complex Instruction Set
Computer (CISC)
Variation in the instruction
size and length of execution
Complex, high level type
instructions
Instructions are executed by
the mico-program
Reduced Instruction Set
Computer (RISC)
About the same in the
instruction size and length of
execution
Basic instructions

Instructions are executed by
the hardware
Parallel method
Using multiple processors simultaneously to execute a
program
Speeds execution
Requires special system software

Parallel method
Multi-processor
Designed to improve performance and
reliability of the system
Multiple processors in parallel with each
processor having a dedicated function
Fault-tolerance
Resource-sharing
Parallel Processing
Super scalar architecture



Super pipeline architecture
Instruction 1 F D E R
Instruction 3 F D E R
Instruction 5 F D E R
Instruction 2 F D E R
Instruction 4 F D E R
Instruction 6 F D E R
Instruction 1 F' F" D' D" E' E" R' R"
Instruction 2 F' F" D' D" E' E" R' R"
Instruction 3 F' F" D' D" E' E" R' R"
Instruction 4 F' F" D' D" E' E" R' R"
Instruction 5 F' F" D' D" E' E" R' R"
Instruction 6 F' F" D' D" E' E" R' R"
Multi-processor
Symmetric Multi-processor
memory is shared among all the processors executing the
same OS.
Competition for the use of memory limits number of
processors that can be connected.
Array processor
High speed scientific computing using pipeline processing
Large scale or dedicated mathematical processors
Deploy pipeline processing principle
Each unit (i.e. processor) is in a queue passing its completed
result to the next unit
Also known as vector processing
Parallel Processing
Multiple processors cooperate with multiple tasks being
performed to execute one job.
SISD (Single Instruction Single Data Stream)
One instruction stream operating on a single data element and is
not parallel
SIMD (Single Instruction Multiple Data Stream)
Each instruction may operate on more than one data element and is
synchronous.
Parallel SIMD
The same instruction is executed by all processors operating on
different sets of data.
MIMD (Multiple Instruction Multiple Data Stream)
Each processor has its own instruction stream acts on its own data
stream independent of the other processors

Processor Performance
Performance
E.g. 500MHz = 500,000,000 pulses per sec
Clock frequency = 1/500MHz = 2ns per pulse
CPI (Cycles Per Instruction)
CPI number of clock ticks required to execute
one instruction
Digital IC
NOT gate
AND gate
OR gate
XOR gate
NAND gate
NOR gate
Half-adder
Full-adder
Flip-flop
Digital IC
Logic Gates
Transistors
Capacitors
Diodes
'NOT' Gate
A NOT A
0 1
1 0
A
'AND' Gate
A B A AND B
0 0 0
0 1 0
1 0 0
1 1 1
A
B
'OR' Gate
A B A OR B
0 0 0
0 1 1
1 0 1
1 1 1
A
B
'XOR' Gate
A B A XOR B
0 0 0
0 1 1
1 0 1
1 1 0
A
B
'NAND' Gate
A B A NAND B
0 0 1
0 1 1
1 0 1
1 1 0
A
B
'NOR' Gate
A B A NOR B
0 0 1
0 1 0
1 0 0
1 1 0
A
B
Exercise 1
Construct the truth
table for the following
circuit
A
B
C
A B C
0 0 1
0 1 0
1 0 0
1 1 1
Exercise 2
Construct the truth
table for the following
circuit
a
1
a
0
L
1
L
2
L
3
L
4
a
1
a
0
L
1
L
2
L
3
L
4
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
Exercise 3
Construct the truth
table for the following
circuit
S
A
B
C
A B S C
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1