PLACEMENT

By:
Patil Puneet
M.Tech Electronics
Row based ASIC
CBIC, MGA and FPGA are row based ASICs.
Most ASICs use two or three metal layers.
With two metal layer
First metal layer for horizontal routing
Second metal layer for vertical routing

Terms & definitions
Channel capacity- max no of horizontal
interconnects that can be placed side by side
Feedthrough
An unused vertical track in a logic cell
Vertical metal strip that runs from top to bottom of
cell, but has no interconnection inside the cell
Electrically equivalent connectors- two
connectors for the same physical net
Crosser cell- is an empty cell that can hold one or
more vertical interconnects.
Interconnect structure in CBIC
Interconnects in MGA
Feedthough pin- an input or output that has
connection at both top & bottom of standard cell
Spacer cell- used to fill space in rows
Alternative connectors- joined inside the logic
cell using high resistance
Electrically equivalent connectors- joined inside
the logic using low resistance
Logically equivalent connector-swapping these
does not alter the logic.
Goals & objectives
Goal is to arrange all the logic cells within the
flexible blocks on a chip
Objectives of the placement steps are to
Guarantee the router can complete routing step
Minimize all the critical net delay
Make chip as dense as possible
Minimize power dissipation
Minimize cross talk between signals
These objectives are difficult to define in a way
that can be solved with as an algorithm
Placement tools use more specific & achievable
criteria, like-
Minimize the total estimated interconnect length
Meet the timing requirements for critical nets
Minimize the interconnect congestion
Measurement of placement goals &
objectives
Trees- graph structures that correspond to
making all the connections for a net
Steiner trees- minimize total length of
interconnects & they are central to ASIC routing
algorithm
Manhattan routing- using inter connects on
rectangular grid.
Euclidean distance- straight line distance
Manhattan distance- rectangular distance
Placement using trees on graph
Complete graph measure
Complete graph- has connections from each
terminal to every other terminal.
Adds all interconnect length of the complete
graph together & divides by n/2, where n is
number of terminal.
Since, no. of connections needed for complete
graph= nC2 =n(n-1)/2
We need only (n-1) interconnects to join n
terminals.
Bounding box- is the smallest rectangle that
encloses all the terminals
Half perimeter measure- is one-half the perimeter
of the bounding box.
It doesnt matter if our
approximations are
inaccurate if there is good
correlation between actual
interconnect length & our
approximation
Wiring length
approximations are functions
of
Number of terminals
Size of bounding box

Interconnect Congestion
Measured by maximum cut line
Placement algorithm
Two classes of placement algorithm commonly
used in commercial CAD
Constructive placement
Iterative placement
Constructive placement method uses set of rules
to arrive at a constructed placement.
Commonly used methods are-
Min-cut algorithm
Eigenvalue method
Min-cut placement
Method uses successive application of partition
Cut the placement area into two pieces
Swap the logic cells to minimize the cut cost
Repeat the process from step 1, cutting smaller
pieces until the logic cells are placed

Eigenvalue placement
Uses cost matrix or weighted connectivity matrix
Cost function f
f=
1
2
c
ij
d
ij
2

,=1

f=x
T
Bx + y
T
By
B is symmetric matrix, the disconnection matrix
Eigenvalues of the disconnection matrix B are the
solutions to our placement problem

Example


Consider the following connectivity matrix C and
its disconnection matrix B
We find the eigenvalues of B are 0.5858, 0.0,
2.0 and 3.4142. The corresponding
eigenvectors are
Iterative placement method
Takes existing placement & tries to improve it by
moving the logic cells.
Several iterative exchange methods that differ in
measurement criteria
Pairwise
Forced-directed interchange
Forced directed relaxation
Force-directed pairwise relaxation
Pairwise-interchange algorithm
Select the source logic cell at random.
Try all the other logic cells in turn as the
destination logic cell.
Use any of the measurement methods to decide on
whether to accept the interchange.
The process repeats from step 1, selecting each
logic cell in turn as a source logic cell.

Placement using simulated annealing
requires so many iterations
Applying simulated annealing to placement, the
algorithm is as follows:
Select logic cells for a trial interchange, usually at
random.
Evaluate the objective function E for the new
placement.
If E is negative or zero, then exchange the logic cells.
If E is positive, then exchange the logic cells with a
probability of exp( E / T ).
Go back to step 1 for a fixed number of times, and then
lower the temperature T according to a cooling
schedule: T
n

+1
= 0.9 T
n
, for example.


Timing driven placement method
Zero slack algorithm
We know the arrival time and required time for
the primary output.
Work forward from primary input and work
backward from primary output.
Difference between required time and arrival
time is slack
Information formats
SDF- to describe the gate delay and interconnect
delay.
PDEF- used by Synopsis to describe placement
information and clustering of logic cells.
LEF- used to define an IC process and a logic cell
library.
DEF- to describe all the physical aspects of a
particular chip design including the netlist and
physical location of cells on chip.
Thank you !