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T
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Gauss-Seidel Pseudo Affine Projection algorithm (GSPAP)
Where the following relations is used
is 1-D vector of length with only one non-zero element at the top of the vector
which is taken as unity.
We solve this linear system using one Gauss-Seidel iteration procedure.
The solution thus obtained is given by
is the desired output signal vector
The filter coefficient update equation is given by
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Double-talk Detection
When v(n) is active, w(n) may diverge
DTD: Detect double-talk quickly
Distinguish double-talk from echo path variations
The Proposed DTD Algorithm
1) Form a error vector with its initial values equal to zero.
2) Keep the new error sample calculated as the difference between the original echo and output of the
adaptive FIR filter of AEC, on the top of the error vector like what we do for the signal vector.
3) Find the norm of the error vector i.e. calculate the error energy or variance.
4) If the error norm is less than a minimum threshold value (say EPSILON = 0.000001), then make the
error norm equal to that value to not to let the norm of the error vector equal to zero or a too low value
5) If the norm of the error vector is less than 0.1 times the norm of the signal vector, which happens when
near end speaker is silent, then the effective step size is made equal to step size times inverse of the
norm of the signal vector as what is done in the NLMS based AEC.
6) If the norm of the error vector is more than 0.1 times the norm of the signal vector, which happens
when near end speaker is speaking, then the step size is made equal to the product of step size and
the inverse of the four times of the sum of the input vector and the error vector norms.
7) Filter coefficient update is done using the update step-size modified in accordance with step 5 or step 6
depending upon whether single talk or double talk scenario.
8) After filter update, the NLP is implemented if the double talk is not detected.
This algorithm is simple, robust and is very quick in determining the presence of double talk or not.
In the simulation, initially single talk situation exists and after a specified duration, near speech signal
which is smaller in length to the far end signal is added to the echo thus error signal contains a mixture
of residual echo and the near end speech signal. After the near end speech signal is over, again the far
end signal alone remains and the error signal containing only the residual echo is observed.
The output signal is recorded and is observed using the WAVOSAUR software. It can be observed
that there exists no divergence of the residual echo during the double talk period and also the
convergence time of the residual echo, after the near end speech signal ends, is also very less.
Fig5:The flowchart for the simulation of the echo canceller algorithm
start
Get far end signal, x(n)
Create echo signal, r(n) from
far end signal
Get near end signal, v(n)
Combine r(n) and v(n) to obtain
Desired signal d(n)
does double talk
exist
Filter loop, filter
Coefficients are frozen
Nlms loop update filter coefficients
Subtract estimated echo from d(n)
to produce residual error signal, e(n)
Do non linear
Processing to
Remove residual
echo
no
YES
Matlab simulation and results
Fig 6 -The far-end signal, echo signal and the residual echo
Fig 7: Far end signal, Residual Echo Signal, error signal for the NLMS method
based Acoustic Echo Cancellation System
Fig 8: Far end signal, Residual Echo Signal, error signal for the VSS-NLMS method based
Acoustic Echo Cancellation System
Fig 9 : Far end signal, Residual Echo Signal, error signal for the GNGD VSS-NLMS method
based Acoustic Echo Cancellation System
Fig 10: Far end signal, Residual Echo Signal, error signal for the GSER VSS-NLMS
method based Acoustic Echo Cancellation System
Comparison between NLMS and Pseudo Affine Projection based Acoustic
Echo Cancellation System
Fig 10: Residual Echo Signal for the NLMS based Acoustic Echo Cancellation System
Fig 11: Residual Echo Signal for the Pseudo Affine Projection method based Acoustic
Echo Cancellation System
Implementation
Software requirements - code compositor studio, visual
studio
System requirements
- IBM pc
- windows XP
- 32 Mbytes RAM and 100 Mbytes hard
disk space
Hardware requirements
-TMS320C6713dsk Digital Signal Processor
- USB cable
Code compositor studio
The Code Composer Studio integrated development environment is used to
build and debug embedded real-time software applications
CCS provides an IDE to incorporate the software tools. it includes tools for
code generation, such as a C compiler, an assembler, and a linker.
CCS includes the following components
- TMS320C67x code generation tools
- CCS IDE
- DSP/BIOS plug-ins and API
- RTDX plug-in, host interface, and API
Code Composer Studio Development process- Code Composer Studio extends
the basic code generation tools with a set of debugging and real-time analysis
capabilities. Code Composer Studio supports all phases of the development
cycle shown here:
Fig 12: code compositor studio setup
Code generation tools
Fig 13: Software development flow
1) Code generation tools
The C compiler
The assembler
The linker
The archiver
assembly translator utility
library-build utility
The run-time-support libraries
The hex conversion utility
The cross-reference lister
The absolute lister
2) CCS Integrated Development Environment (IDE)
The Code Composer Studio Integrated Development Environment (IDE) is
designed to allow you to edit, build, and debug DSP target programs.
3) DSP/BIOS is a scalable real-time kernel. It is designed for applications that require real-time
scheduling and synchronization, host-to-target communication, or real-time instrumentation.
4) RTDX plug-in, host interface, and API- Real-Time Data Exchange (RTDX) provides real-
time, continuous visibility into the way target applications operate in the real world. RTDX
allows system developers to transfer data between a host and target devices without interfering
with the target application
Programming in CCS
Developing a Simple Program on CCS
Debugging a Project using CCS
Additional features of CCS
Creating a New Project
Adding Files to a Project
Building and Running the Program
Using Break Points and the Watch Window
Adding a Probe Point for File I/O
Displaying Graphs
TMS320C6713dsk
Digital signal processors such as the TMS320C6x (C6x) family of processors are
like fast special-purpose microprocessors with a specialized type of architecture and
an instruction set appropriate for signal processing.
The C6x notation is used to designate a member of Texas Instruments (TI)
TMS320C6000 family of digital signal processors.
Based on VLIW architecture and floating point processor.
Typical Applications for the TMS320 Family in telecommunications, automotive,
control system, military, medical, instrumentation and in image processing.
Package Contents of tms320c6713dsk
Block diagram of TMS320C6713 DSK
Fig 15 : block diagram of TMS320C6713dsk
TMS320C6713 DSP features
A Texas Instruments TMS320C6713 DSP operating at 225 MHz
An AIC23 stereo codec
8 Mbytes of synchronous DRAM
512 Kbytes of non-volatile Flash memory (256 Kbytes usable in default
configuration)
4 user accessible LEDs and DIP switches
Software board configuration through registers implemented in CPLD
Configurable boot options
JTAG emulation through on-board JTAG emulator with USB host
Single voltage power supply (+5V)
Fig 16- Board Diagram of TMS320C6713 DSK
Board Components
CPLD (Programmable Logic)
AIC23 Codec
Synchronous DRAM
Flash Memory
LEDs and DIP Switches
Daughter Card Interface
Block diagram of hardware
ERLE curve for NLMS,VSS nlms based AEC with white
Gaussian noise samples as the far-end input
NLMS
VSS-NLMS
ERLE curve for NLMS,VSS nlms based AEC with white
Gaussian noise samples as the far-end input
RR VSS-NLMS
GNGD VSS-NLMS
ERLE curve for NLMS,VSS nlms based AEC with white
Gaussian noise samples as the far-end input
GESR VSS-NLMS
NSCE curve for NLMS,VSS-NLMS based AEC with white
Gaussian noise samples as the far-end input
NLMS
VSS-NLMS
NSCE curve for NLMS,VSS-NLMS based AEC with white
Gaussian noise samples as the far-end input
RR VSS-NLMS
GNGD VSS-NLMS
NSCE curve for NLMS,VSS-NLMS based AEC with white
Gaussian noise samples as the far-end input
GESR VSS-NLMS
Conclusion and future work
The Scope of this project is to implement Acoustic Echo Cancellers based on various
adaptive filtering methods.The implementations are to be done using
TMS320C6713DSK for each AEC and the performances have to be evaluated for
comparison.
Many parameters occur in algorithm such as step size, regularization parameter, safety
constant etc used to achieve target performance. the parameter tuning gains an
important role in simulation process.
In recent applications like acoustic echo cancellation, the order of the impulse response
to be estimated is very high, and these traditional approaches are inefficient and real
time implementation becomes difficult. .
This approach, referred to as sub-band adaptive filtering, is expected to reduce not only
the computational complexity but also to improve the convergence rate of the adaptive
algorithm
But in practice, different sub-band adaptive algorithms have to be used to enhance the
performance with respect to complexity, convergence rate and processing delay.
A single sub-band adaptive filtering algorithm which outperforms the full band scheme
in all applications is yet to be realized.
The Perfect Reconstruction Filter Bank (PRFB) is used to model the linear FIR system.
The structure offers efficient implementation with reduced arithmetic complexity.
references
1.Srinivasaprasath Raghavendran Implementation of an Acoustic Echo Canceller Using Matlab
2. ITU-Ts G.167 Acoustic Echo Cancellers
3. Lu Lu Implementation of Acoustic Echo Cancellation for PC Applications
4. Ahmed I. Sulyman & Azzedine Zerguine Echo Cancellation Using a Variable Step-Size
NLMS Algorithm
5. Junghsi Lee, Jia-Wei Chen, and Hsu-Chang Huang Performance Comparison of
Variable Step-Size NLMS Algorithms
6. Y. S. Choi, H. C. Shin, and W. J. Song, Robust regularization for normalized LMAlgorithms,
IEEETransactions on Circuits and Systems II, Express Briefs, Vol. 53, No. 8, pp. 627
631, Aug. 2006.
7. D. P. Mandic, A generalized normalized gradient descent algorithm, IEEE Signal Processing
Letters, Vol. 11, No. 2, pp. 115118, Feb. 2004.
8. J. Lee, H. C. Huang, and Y. N. Yang, The generalized square-error-regularized LMS
Algorithm, Proceedings of WCECS 2008, pp. 157 160, Oct. 2008.
9. F. Bouteille, P. Scalart, M. Corazza, Pseudo Affine Projection Algorithm New Solution for
Adaptive Identification, Eurospeech, 1999
10. Texas Instruments, TMS320C6713 DSK, Floating-Point Digital Signal Processors, Data
Sheet, Dallas, TX, June 2006
11. Spectrum Digital, TMS320C6713 DSK Technical Reference, INC. 12502 Exchange Drive,
Suite, November 2003
12. TIs Code Composer Studio (CCS) Users Guide