Inter Integrated Circuit Bus Protocol

(I
2
C)


By: Prof. Mitesh Limachia






Need of Serial Bus Protocol
Peripheral devices in embedded systems =>
parallel address and data bus => lots of wiring and
requires number of pins => additional decoding logic
required.

To reduce the pins and wiring => cost => Serial bus
protocol => SPI (4-wire) & I
2
C (2-wire).

Penalty => Slower communication.




Various Serial Bus Protocols
UART
SPI Embedded System Protocol
I
2
C- Embedded System Protocol
I
2
S- Audio/Sound Bus Protocol
CAN
USB
SATA etc..
I
2
C bus => Philips, consumer products (TV)

Originally intended for operation on one single
board (PCB)

Today, variety of devices are available with
on-chip I
2
C interface. i.e Microcontroller,
E
2
PROM, A/D converters etc.
I
2
C Bus Characteristics

Two wires, SDA, SCL carry information between
devices connected on bus

Every device is identified by unique address
(7-bit slave address)

Synchronous, Half-duplex serial communication

Device => Transmitter or Receiver => functionality
i.e LCD device, Receiver. Memory, Transmitter or
Receiver.

Unique Start and Stop conditions
Multi-Master Capability

Bi-directional data transfer

Acknowledgement after each transferred byte

No fixed length of transfer

No chip enable (Slave Select Signal, SPI) is required.



I
2
C Bus Terminology
Term Description
Transmitter Device which send data to bus
Receiver Device which receives data from bus
Master Device which initiates transfer, generate CLK signal to
permit data transfer and stop data transfer
Slave Device addressed by Master
Multi-Master More than one Master control bus at same time
Arbitration Procedure to allow One Master among Multi-Master,
Winning message is not corrupted
Realization
9 of 40
I
2
C Bus Configuration Example

DATA Transfer on the I
2
C Bus
In normal data transfer, the data line (SDA) only
changes state when the clock (SCL) is low.
SDA
SCL
Data line stable;
Data valid
Change
of data
allowed
Start and Stop Conditions
A transition on the data line while the clock line is high is
defined as either a start or a stop condition.

Both start and stop conditions are generated by the bus master

The bus is considered busy after a start condition, until a stop
condition occurs
Start
Condition
Stop
Condition
SCL SCL
SDA
SDA
Addressing Scheme
Master => 7-bit address => device which it want to access.

Every devices, hook up on bus=> own unique address.

After START condition, 7-bit address sent along with data
direction bit (R/W)

Always, first byte of data transfer.

MSB
ACK
LSB
7 Bit Slave Address
R / Wr
First Byte in Data Transfer on the I
2
C Bus
R/W
0 Slave written by Master
1 Slave read by Master

ACK Generated by the slave whose address has been output
By Slave
MASTER
SLAVE
Data Transfer on the I
2
C Bus
Start Condition
Slave address + R/W
Slave acknowledges with ACK (9
th
SCK)
All data bytes
Each followed by ACK
Stop Condition
ACK from
Slave
ACK from
Slave
Remember : Clock is produced by Master
Start
Stop
SCL
SDA
Repeated START Condition
A repeated Start avoids releasing the bus and therefore prevents
another master from taking control over the bus.
21 of 40
I
2
C Bus Configuration Example
Multi-Master Capability
Two Master can begin transmitting on an idle bus at
the same time. Method deciding which take control of
the bus and completes its transmission.

Arbitration (SDA Line)

Clock Synchronization (SCL Line)

23 of 40
Arbitration Between Two Masters
As the data line (SDA) is like a wired AND,
ZERO address bit overwrites a ONE address bit.
Bit by Bit, During every bit, while SCL is high each master
checks to see SDA level matches with what it has sent.



25
Two or more masters may generate a START condition at the same time
Arbitration is done on SDA while SCL is HIGH - Slaves are not involved
DATA2

DATA1

SCL

0
0
0
SDA

0
START 1 0
Master? loses arbitration
0
0
1
0
1 1 0
Example-2
Clock Synchronization
CLK Synchronization => Wired-AND function on SCL line.

SCL line => held Low by Master with longest LOW period,
Master with shorter LOW periods enter HIGH wait-states
during time.



I
2
C Bus
Configuration
on
LPC2300 kit
I
2
C Control Set Register
(I
2
CONSET)

Bit Symbol Value Description
7 - Reserved for further use.

6 I2EN I
2
C Interface enable.
1 I
2
C interface enable
0 SDA and SCL i/p signals are
ignored.

I
2
C Control Set Register
(I
2
CONSET)

Bit Symbol Value Description
5 STA START flag
1 I
2
C interface to enter into
Master mode and transmit a
START condition.

I
2
C interface enter master transmitter mode when
software sets STA bit.
I
2
C interface will send the START cond. as soon as the
bus is free.
ACK from
Slave
ACK from
Slave
Start
Stop
SCL
SDA
By I
2
C hardware
I
2
C Control Set Register
(I
2
CONSET)

Bit Symbol Value Description
4 STO STOP flag
1 Master mode, STOP
condition is transmitted on
I
2
C bus.
When bus detects STOP
condition, STO is cleared
automatically.
I
2
C Control Set Register
(I
2
CONSET)

Bit Symbol Value Description

3 SI I
2
C interrupt flag
1 Bit is set by I
2
C interface
H/W when state
changes
occur.

SI must be reset by S/W (application program).
I
2
C Control Set Register
(I
2
CONSET)

Bit Symbol Value Description

2 AA 1 ack received during ack
clock pulse (9
th
) on SCL line
(1) Slave address received
(2) data byte is received while I
2
C
is in master receiver mode
(3) While I
2
C is in slave
receiver mode

I
2
C Control Set Register
(I
2
CONSET)

1:0 - Reserved for further use.

I
2
C Control Clear Register(I2CCONCLR)
I
2
C Status Register
(I2STAT)

Bit Symbol Value Description
2:0 --- Reserved
7:3 Status Status information about
I
2
C interface.
26 possible status codes.
I
2
C Data Register (I2C DAT)
Bit Symbol Value Description
7:0 Data -Holds data values, received
or transmitted.
-Data shifted from right to left
(MSB first)
MASTER
I
2
C
H/W
Interface
Application
Program
SDA
SCLK
ACK from
Slave
ACK from
Slave
Start
Stop
SC
L
SD
A
State Changed
SI=1 in I
2
CONSET
SLA+W
I
2
C Slave Address Register
Bit Symbol Value Description
7:1 Address I
2
C device address for
slave mode
0 GC General Call enable bit
I
2
C Operating Modes
Master Transmitter mode
Master Receiver mode
Slave Transmitter mode
Slave Receiver mode

MASTER TRANSMITTER

START
I
2
CONSET=0x60 (I
2
C enable & START bit)
Read I
2
CONSET
SI=1?
Read I
2
CSTAT
I
2
CSTAT=
0x08?
Load Slave Address +R/W bit into I
2
DAT
Clear SI and STA bit in I
2
CONCLR=0X28
A
Fault Handler
yes
yes
No
No

A
Read I
2
CONSET
Read I
2
CSTAT
N= Number of byte transmitted
Load data into I
2
DAT
A
SI=1?
I
2
CSTAT=
0x18?
Clear SI & STA bit in I
2
CONCLR=0X28
B
Fault Handler
yes

A
Read I
2
CONSET
SI=1?
Read I
2
CSTAT
I
2
CONSET =0X10 (STOP cond) & also clear SI)
A
N=0?
I
2
CSTAT=
0x28?
B
yes
Fault Handler
NO
yes

A
Read I
2
CONSET
STO=0?
END
yes
Sample C-Code
Address=0x74,
DAC
Data=0x55
#include<lpc2300.h>
Void init (void);


Define SI (1<<4)
Void ISR_8(void)
Void ISR_18(void)
Void ISR_28(void)

int (main)
{
init();
I
2
CONSET=0x60;// START condition.


Void init()
{
PINSEL0=0x50;//SCL line &
SDA

I2CONCLR=0x6C//clearing all
flags

I2CONSET=0x40//enable I
2
C
interface

I2SCLH=0xC;//100 KHZ
I2SCLL=0xD;
}



label: While(!(I
2
CONSET& SI));

int temp=0;
temp=I2STAT;
switch (temp)
{
Case8:
ISR_8(); // state routine
goto label

Case24:
ISR_18(); // state routine
goto label

Case40:
ISR_28(); // state routine
goto label
deault :
break;
} While(1) {}
}

Void ISR_8( ) //start condition is transmitted
{
I
2
DAT=0x74;// slave address + W;
I
2
CONCLR=0x28;//clear SI and START flag
}

Void ISR_18( ) //ack received from slave for slave address
{
I
2
DAT=0x55;// load data
I
2
CONCLR=0x8;// clear SI
}

Void ISR_28( )
{
I
2
CONSET=0x10;//Transmitt STOP condition.
I
2
CONCLR=0x8;//clear SI
}

Comparison between I
2
C & SPI
Parameter I
2
C SPI
Speed 100/400 kbps 1MBPS
Number of Pins 2-wire 4-wire
Complexity More Less
Multi Master
Capability
Yes No
Reliability (data
transmission)
Higher Lower
Flow Control Yes No
More devices on board Preferred Not Preferred
Power Efficiency Lower
(pull-up Resistors)
Higher
Syllabus
Memory Interfacing - ARM Reference Manual
-Bus Cycle Type onwards

8.2 AHB & APB Bus interface Steve Furber

VIC LPC23xx.pdf

I
2
C- LPC23xx.pdf

Self Study 8.5, 8.6 (Steve Furber) - Block Examination