Final Exam Project

4 bit Full Adder Layout and Analysis

using Lasi and WinSpice
Assignment Objectives
Do a hierarchal layout of a half
adder, full adder and 4 bit adder
using LASI, then simulate the circuit
using SPICE to make sure that the
design will work.
Overview
Hierarchal Layout design is done
using Lasi.
N3X2, P3X2, NAND, XOR, Half-Adder,
Full-Adder and 4 bit Full Adder
layouts are made in hierarchal
sfashion using bottom up approach.
Each Cell is analyzed by using
Winspice3 .CIR file created by Lasi.
P3X2 (Rank 1)Cell- Standard cell from Lasi
Library
N3X2 (Rank 2) Cell -Standard cell from Lasi
Library
INVERTER (Contd)
Inverter cell has Rank 2.
Inverter cell is made using
P3X2 and N3X2 cell.
It is used to provide A and B
for XOR input and NAND input
to make OR gate.Also it is
used at output of a NAND to
make AND.
INVERTER
NAND (Contd)
NAND cell has rank 2.
It is used to make AND gate and OR
gate.
NAND
XOR (Contd)
XOR cell has Rank 2.
It is is made to provide sum of Half Adder.
It is little different than regular XOR because it
requires four inputs A, A, B, and B.
By designing in with four inputs we simplify
design and reduced transistors.
XOR
Half-Adder (Contd)
Half-Adder has rank 3.
It is designed using INVERTER, NAND and
XOR gate.
Sum = AB + BA.
Carry = AB.

Half-Adder
Full-Adder (Contd)
It has rank 4.
Full adder is made using two HALF-
ADDER , 2 Inverter and a NAND gate.
S1 = HA(A,B)
Sum = HA(S1,Carry In)
Carry = OR(Carry 1,Carry 2)
Full-Adder
4 Bit Full Adder (Contd)
It has rank 5.
It is made using four 1 bit Full-Adder.
First Full-Adder has Carry in 0.
4
th
Carry out is Final Carry out of 4 bit Full-
Adder.
4 Bit Full Adder
SPICE SIMULATION
Each cell is compiled using LasiCkt.
Generate .CIR files used in WinSpice3 for
simulation of circuit.
Every analyzed signal is offset by 6V to
see each signal properly.
INVERTER Simulation (Contd)
Next slide shows screen
capture of Inverter simulation.
A_ is output of signal input
signal A.

INVERTER Simulation
NAND Simulation (Contd)
Next slide show simulation of
NAND gate.
AB_ is output of NAND gate.
11,10,01,00 signals analyzed.
NAND Simulation
XOR Simulation (Contd)
Next slide show simulation of XOR
gate.
AXORB is output of XOR gate.
11,10,01,00 signals analyzed.
It is Sum of Half-Adder.
XOR Simulation
Half-Adder Simulation (Contd)
Next slide show simulation of Half-
Adder gate.
S is Sum and C is carry.
11,10,01,00 signals analyzed.

Half-Adder Simulation
Full-Adder Simulation(Contd)
Next slide show simulation of full adder.
All the combination from 000 to 111 is
used as Cin, B and A inputs.
Full-Adder Simulation
4 Bit Full Adder Simulation (Contd)
Next four slides shows simulation of 4 bit
Full Adder.
Individual plot used each inputs for proper
demonstration.
VN4 is Carry out 1.
VN5 is Carry out 2.
VN6 is Carry out 3.

4 Bit Full Adder Simulation- A0+B0 (Contd)
4 Bit Full Adder Simulation- A1+B1 (Contd)
4 Bit Full Adder Simulation- A2+B2 (Contd)
4 Bit Full Adder Simulation- A3+B3 (Contd)
Related Documents
Included floppy contains two directories LASI and CIR.
LASI Directory Contains all the Layout files and other
required files to open layouts in LASI .
To open LASI Layout files create shortcut of LASI
executable file, and change the Start in option through
properties to A:\ LASI \.
Circuit simulation .CIR files are located in CIR directories.