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EE 587
SoC Design & Test
Partha Pande
School of EECS
Washington State University
pande@eecs.wsu.edu
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System Design Issues
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Low Energy FPGA Architecture
Architectural level optimization
Level 0 Nearest Neighbor
Level 1 Mesh
Level 2 - Hierarchical
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Different Architectures
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Paths in Interconnect
Connection may be long, complex:
LE LE LE LE LE
LE LE LE LE LE
LE LE LE LE LE
Wiring channel
W
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r
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n
g

c
h
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l

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Interconnect Architecture
Connections from wiring channels to LEs.
Connections between wires in the wiring channels.
LE LE
Wiring channel
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Switchbox
channel channel
c
h
a
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l

c
h
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Mesh-based Interconnect Network
Switch Box
Routing of the data
Connect Box
Connects cell I/Os
To the global
interconnect

Interconnect
Point
Courtesy Dehon and Wawrzyniek
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Circuit Level Optimization
The connecting path from one CLB to
another is an RC chain
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Low Swing Interconnect
Mode E (pj) D (ns) ED
Full Swing 72.3 1.9 137
Low Swing 31.4 2.3 72
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Low Power SRAM Design
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Memory Organization
Sense amplifiers/drivers
Column decoder
A
K
A
K-1


A
L-1
Storage cell
Word line
Bit line
Input-Output (M bits)
A
0

A
K-1
2
L-K
M.2
K
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SRAM Cell
bit
bit
VDD
Sense
amplifier
PC
EQ
Output
BL
BL
WL
Precharge
circuit
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Cell Array Power Management
Smaller transistors
Low supply voltage
Lower voltage swing (0.1V 0.3V for SRAM)
Sense amplifier restores the full voltage swing for outside
use.
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SRAM Cell Design
6 transistor SRAM cell reduces static current
(leakage) but take more area
V
th
reduction in very low V
dd
SRAMs suffer from
large leakage current

Use multiple threshold devices:
Memory cell with high V
th
(reduce leakage)
Peripheral circuits with low V
th
(improve speed)

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Banked Organization
Banking targets total switched capacitance to achieve reduced
power and improved speed

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Divided Word Line
Main idea: Divide each row of RAM cells into segments (blocks), use a
decoder to access only one segment
Only the memory cells in the activated block have their bit line pair
driven
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Divided Word Line
Pros:
Improves speed (by decreasing word line delay)
Lower power dissipation (by decreasing the number of bit
line pair activated)
However, local decoders add delay
Less cells/block reduces power, but increases area (more local
decoders)
Chang, 1997:
49.8% power reduction, 14.8% area penalty
82.9% power reduction, 24.8% area penalty

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Reduced Bit Line Swing
Limit voltage swing on bit lines to improve both speed and
power:
1. Pulsed word line
2. Bit line isolation

Need sense amplifiers for each column to sense/restore
signal
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Pulsed Word Line
Main idea: Isolate memory cells
from the bit lines after sensing,
to prevent the cells from
changing the bit line voltage
further
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Pulsed Word Line
Q
R S
Reset from dummy sense-amp Word enable
SA Sense Amplifiers
Memory Core
Accessed Row
D
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m
m
y

C
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n
W
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d

D
r
i
v
e
r
W
o
r
d

D
e
c
o
d
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r
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Pulsed Word Line
Dummy bit lines reach full swing, but trigger pulse shut off when regular
bit lines reach 10% swing
Generation of word line pulses very critical
Too long: power efficiency degraded
Too short: Sense amplifiers operation may fail
Generation of word line using delay lines is susceptible to process and
temperature

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Bit Line Isolation
Main idea: Isolate sense amplifiers from bit line after sensing, to
prevent from having large voltage swings

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Row Decoders
Collection of 2
M
complex logic gates
Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder
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Hierarchical Decoders


A
2
A
2
A
2
A
3
WL
0
A
2
A
3
A
2
A
3
A
2
A
3
A
3
A
3
A
0
A
0
A
0
A
1
A
0
A
1
A
0
A
1
A
0
A
1
A
1
A
1
WL
1
Multi-stage implementation improves performance
NAND decoder using
2-input pre-decoders
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Data Retention in SRAM
(A)
1.30u
1.10u
900n
700n
500n
300n
100n
0.00 .600 1.20 1.80
Factor 7
0.13 m CMOS
m
0.18 m CMOS m
V
DD
I
l
e
a
k
a
g
e

SRAM leakage increases with technology scaling
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Reducing Retention Current
Turning off unused memory blocks
Increasing the thresholds by using body biasing
Inserting extra resistance in the leakage path
Lowering the supply voltage
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Suppressing Leakage in SRAM
SRAM
cell
SRAM
cell
SRAM
cell
V
DD,int
V
DD
V
DD
V
DDL
V
SS,int
sleep
sleep
SRAM
cell
SRAM
cell
SRAM
cell
V
DD,int
sleep
low-threshold transistor
Reducing the supply voltage Inserting Extra Resistance