Fault models

Stuck-at-0
0
1
Stuck-at-1
Reset coupling 0 0 Set coupling 1
0
1 1
Inversion coupling 0 1 1
0
Transition /0 0 1 Transition /1
ADR
0 0 Inversion coupling 1 1
0
1
AND bridging 0 1
0 0
1 0 OR bridging 1 1
Neighborhood
pattern sensitive
faults (active)
0
1 0 1
1
0 1
Neighborhood
pattern sensitive
faults (passive)
1
1 1 0
0
0
Address decoder
faults
ADR ADR ADR ADR
Elements of march test
(w0)








x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
0
(r1,w0)
1
1
1
1
1
1
1
1
(w1)








(r0,w1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
C - algorithm
Number of steps: 10n
Fault coverage: AFs, SAFs, TFs, CFins , CFids
(w0)








(r1,w0)
1
1
1
1
1
1
1
1
(r0,w1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
(r0,w1)
0
0
0
0
0
0
0
0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
(r1,w0)
1
1
1
1
1
1
1
1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
(r0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Checkerboard test and data retention
Designed to test refresh
operations of DRAMs
Maximizes leakage current
and detects leakage faults
Used as data retention test
To be effective it must
consider address
scrambling and layout
1 0 1 0
0 1 0 1
0 1 0 1
1 0 1 0
Data backgrounds for word memories
Multiple data backgrounds to detect coupling and
bridging faults between cells of the same word
For every pair of cells all four combinations are
checked
2 (log
2
w + 1) backgrounds
16 backgrounds for
128-bit wide memory
Normal and inverse

D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1
1 1 1 1 0 0 0 0
0 0 1 1 0 0 1 1
1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
1 0 1 0 1 0 1 0
Data in word-oriented memory
(w0) (r1,w0) (r0,w1) (r0,w1)
Parallel memory BIST

BIST
mode
Clock
System logic
Address generator
F
S
M
Data generator
Control generator
Start
Hold
Done
Fail
Memory
Serial memory BIST
System logic
Data output

Serial output
Serial input
Address M
0 0 0 0
r0 0 0 0 0
w1 1 0 0 0
r0 1 0 0 0
w1 1 1 0 0
r0 1 1 0 0
w1 1 1 1 0
r0 1 1 1 0
w1 1 1 1 1
r1 1 1 1 1
Minimal logic and routing
Longer test time
Memory
Serial-parallel data interface trade-offs
Memory
Memory Memory
Memory
Memory BIST collar
+
Memory BIST
controller
To / From
TAP controller
Embedded memory BIST collar
mux address / control bus and data lines
local comparator with single pass/fail
local data generator to reduce routing
area and timing problems
local address validation
Memory controller at the top level
TAP controller as test engine
Memory
array
Functional logic
Shared controller and parallel test
Insert collars
Connect them
through memory
test bus
to memory BIST
controller
to TAP
+
Memory BIST
controller
To / From
TAP controller
Memory
array
+
Memory
array
Functional logic
Parallel memory BIST collar
Memory array
Data in Address Data out Ctrl
MBIST mode


Sin
Sout
Clock
= ?
Functional address
BIST address
Functional data
BIST data
Pass / Fail
B
I
S
T

c
o
n
t
r
o
l

F
u
n
c
t
i
o
n
a
l

c
o
n
t
r
o
l

Full-Speed test application
Runs at system clock speeds with single cycle
read/write operations
Uncovers speed-related defects
Reduce test application time.
Addr/Cntrl/
Data
Clock
Memory
Output
Compare
Circuitry
Circuit
Output
Write
Clock
Cycle 1
Clock
Cycle 2
Clock
Cycle 3
Clock
Cycle 4
Clock
Cycle 5
Setup
Read 1
Setup
Write 1
Setup
Read 2
Setup
Read 3
Setup
Write 2
Compare
Read 1
Write 1

Read 2 Read 3
Compare
Read 2
Pass/Fail
Read 2
Pass/Fail
Read 1
Compare
Read 3
Read 1
Diagnostics
Detect failing location/data during test
Should diagnose speed related defects
Two types - Hold and resume, Hold and restart
How it works?
BIST controller stops after 1 (or 2) failures
Fail data is scanned out
BIST session resumes from where it stops (Hold and
resume)
BIST session restarts after fail data is scanned out
(Hold and restart)

Full-speed diagnostics
+
Memory
array
MBIST
controller
ATE
Restart
Diagnostic monitor
Yield improvement with memory redundancy
Memory percentage, defect rate, and redundancy
amount affect yield
Source: Zorian, Rodgers, DATE 2002
Redundancy Yield Improvement
0
10
20
30
40
50
60
70
80
90
100
0 10 20 30 40 50 60 70 80 90 100
Chip Memory Percentage
M
e
m
o
r
y

Y
i
e
l
d

Optimal
Level 3
Redundancy
Level 2
Redundancy
Level 1
Redundancy
No Redundancy
+
Memory BIST
controller
Memory
Array
Redundancy and repair
Extra columns, rows, or rows
and columns
At the end of test - good,
repairable, or non-repairable
Repair data scanned out at
the end of test
Full-Chip memory BIST integration


Assign memories to
controller
(BIST Scheduling)
Memory BIST Generation
(Generate Controller/Collars)
BIST GENERATION
Read in SOC netlist
Identify memories
Insert controllers in the design
Stitch controllers to top-level
BIST INSERTION
Full Chip Memory BIST Control
Block
BIST Block
BIST Block
BIST
Controller
Memory 1
Memory 2
SOC
TDO
MBIST Data
Register
TDI
CLK
TM S
TCK
TRST
TAP Controller
rst_l
test_h
test_done
fail_h
Boundary Scan Register
Programmable algorithms
Selection of algorithms
March1, March2, March3, Unique Address, Checkerboard,
address jumping
Synthesizable algorithms
user defined prior to synthesis
simple language
number of sequences, backgrounds, sequence elements etc.,
Programmable algorithms
defect mechanisms may not be known before fabrication
memory BIST controller implements a class of algorithms
field programmable parameters define active elements of test
sequences
Summary
Key components of a BIST controller
algorithm controller
data background generator
address generator
comparator
Very high quality test of embedded arrays
BIST controller shared across a number of memory
arrays to reduce area
BIST diagnostics helps in gathering failure
information
Built-in repair results in yield improvement