Introduction To Cmos Vlsi Design: DC & Transient Response

Introduction to
CMOS VLSI
Design

Lecture 4:
DC & Transient Response
David Harris

Harvey Mudd College
Spring 2004
CMOS VLSI Design 4: DC and Transient Response Slide 2
Outline
DC Response
Logic Levels and Noise Margins
Transient Response
Delay Estimation
Activity
1) If the width of a transistor increases, the current will
increase decrease not change
2) If the length of a transistor increases, the current will
3) If the supply voltage of a chip increases, the maximum
transistor current will
4) If the width of a transistor increases, its gate capacitance will
5) If the length of a transistor increases, its gate capacitance will
6) If the supply voltage of a chip increases, the gate capacitance
of each transistor will

Activity
1) If the width of a transistor increases, the current will
2) If the length of a transistor increases, the current will
3) If the supply voltage of a chip increases, the maximum
transistor current will
4) If the width of a transistor increases, its gate capacitance will
5) If the length of a transistor increases, its gate capacitance will
6) If the supply voltage of a chip increases, the gate capacitance
of each transistor will

DC Response
DC Response: V
out
vs. V
in
for a gate
Ex: Inverter
When V
in
= 0 -> V
out
= V
DD
When V
in
= V
DD
-> V
out
= 0
In between, V
out
depends on
transistor size and current
By KCL, must settle such that
I
dsn
= |I
dsp
|
We could solve equations
But graphical solution gives more insight

I
dsn
I
dsp
V
out
V
DD
V
in
Transistor Operation
Current depends on region of transistor behavior
For what V
in
and V
out
are nMOS and pMOS in
Cutoff?
Linear?
Saturation?
nMOS Operation
Cutoff Linear Saturated
V
gsn
<

V
gsn
>

V
dsn
<

V
gsn
>

V
dsn
>

I
dsn
I
dsp
V
out
V
DD
V
in
nMOS Operation
V
gsn
< V
tn

V
gsn
> V
tn

V
dsn
< V
gsn
V
tn

V
gsn
> V
tn

V
dsn
> V
gsn
V
tn

I
dsn
I
dsp
V
out
V
DD
V
in
nMOS Operation
V
gsn
< V
tn

V
gsn
> V
tn

V
dsn
< V
gsn
V
tn

V
gsn
> V
tn

V
dsn
> V
gsn
V
tn

I
dsn
I
dsp
V
out
V
DD
V
in
V
gsn
= V
in
V
dsn
= V
out
nMOS Operation
V
gsn
< V
tn
V
in
< V
tn
V
gsn
> V
tn
V
in
> V
tn
V
dsn
< V
gsn
V
tn
V
out
< V
in
- V
tn
V
gsn
> V
tn
V
in
> V
tn
V
dsn
> V
gsn
V
tn
V
out
> V
in
- V
tn
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsn
= V
in
V
dsn
= V
out
pMOS Operation
V
gsp
>

V
gsp
<

V
dsp
>

V
gsp
<

V
dsp
<

I
dsn
I
dsp
V
out
V
DD
V
in
pMOS Operation
V
gsp
> V
tp

V
gsp
< V
tp

V
dsp
> V
gsp
V
tp

V
gsp
< V
tp

V
dsp
< V
gsp
V
tp

I
dsn
I
dsp
V
out
V
DD
V
in
pMOS Operation
V
gsp
> V
tp

V
gsp
< V
tp

V
dsp
> V
gsp
V
tp

V
gsp
< V
tp

V
dsp
< V
gsp
V
tp

I
dsn
I
dsp
V
out
V
DD
V
in
V
gsp
= V
in
- V
DD
V
dsp
= V
out
- V
DD
V
tp
< 0

pMOS Operation
V
gsp
> V
tp
V
in
> V
DD
+ V
tp
V
gsp
< V
tp
V
in
< V
DD
+ V
tp
V
dsp
> V
gsp
V
tp
V
out
> V
in
- V
tp
V
gsp
< V
tp
V
in
< V
DD
+ V
tp
V
dsp
< V
gsp
V
tp
V
out
< V
in
- V
tp
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsp
= V
in
- V
DD
V
dsp
= V
out
- V
DD
V
tp
< 0

I-V Characteristics
Make pMOS is wider than nMOS such that |
n
= |
p
V
gsn5
V
gsn4
V
gsn3
V
gsn2
V
gsn1
V
gsp5
V
gsp4
V
gsp3
V
gsp2
V
gsp1
V
DD
-V
DD
V
dsn
-V
dsp
-I
dsp
I
dsn
0
Current vs. V
out
, V
in
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
Load Line Analysis
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
For a given V
in
:
Plot I
dsn
, I
dsp
vs. V
out
V
out
must be where |currents| are equal in
I
dsn
I
dsp
V
out
V
DD
V
in
Load Line Analysis
V
in0
V
in0
I
dsn
, |I
dsp
|
V
out
V
DD
V
in
= 0
Load Line Analysis
V
in1
V
in1
I
dsn
, |I
dsp
|
V
out
V
DD
V
in
= 0.2V
DD

Load Line Analysis
V
in2
V
in2
I
dsn
, |I
dsp
|
V
out
V
DD
V
in
= 0.4V
DD
Load Line Analysis
V
in3
V
in3
I
dsn
, |I
dsp
|
V
out
V
DD
V
in
= 0.6V
DD
Load Line Analysis
V
in4
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
V
in
= 0.8V
DD
Load Line Analysis
V
in5
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
V
in
= V
DD
Load Line Summary
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
DC Transfer Curve
Transcribe points onto V
in
vs. V
out
plot
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
V
out
V
DD
C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp
Operating Regions
Revisit transistor operating regions
C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp
Region nMOS pMOS
A
B
C
D
E
Operating Regions
Revisit transistor operating regions
C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp
Region nMOS pMOS
A Cutoff Linear
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff
Beta Ratio
If |
p
/ |
n
= 1, switching point will move from V
DD
/2
Called skewed gate
Other gates: collapse into equivalent inverter
V
out
0
V
in
V
DD
V
DD
0.5
1
2
10
p
n
|
|
=
0.1
p
n
|
|
=
Noise Margins
How much noise can a gate input see before it does
not recognize the input?
Indeterminate
Region
NM
L
NM
H
Input Characteristics Output Characteristics
V
OH
V
DD
V
OL
GND
V
IH
V
IL
Logical High
Input Range
Logical Low
Input Range
Logical High
Output Range
Logical Low
Output Range
Logic Levels
Logic levels are defined at unity gain point of DC
transfer characteristic to give conservative bound on
worst case static noise margin
V
DD
V
in
V
out
V
OH
V
DD
V
OL
V
IL
V
IH
V
tn
Unity Gain Points
Slope = -1
V
DD
-
|V
tp
|
|
p
/|
n
> 1
V
in
V
out
0
Noise Margins (cont)
Noise margins values specified in CMOS datasheets
for IOs. From Texas Instruments OMAP CPU
(Vdd=1.8V)
V
IL
= 0.35Vdd (max), V
IH
= 0.65Vdd (min)
V
OL
= 0.2 (max), V
OH
= Vdd 0.2 (min)
Noise margin Low (NM
L
), Vdd = 1.8 V
NM
L
= V
IL
V
OL

NM
L
= 0.35*1.8 0.2 = 0.63 0.2 = 0.43V
Noise margin high (NM
H
), Vdd = 1.8 V V
NM
H
= V
OH
V
IH

NM
H
= (1.8 0.2) (0.65*1.8) = 1.6 -1.17 = 0.43V

Transient Response
DC analysis tells us V
out
if V
in
is constant
Transient analysis tells us V
out
(t) if V
in
(t) changes
Requires solving differential equations
Input is usually considered to be a step or ramp
From 0 to V
DD
or vice versa
Inverter Step Response
Ex: find step response of inverter driving load cap
0
( )
(
)
)
(
o
i
ut
n
out
V t t
t
V
t
V
d
d
t
=
< =
=
V
in
(t)
V
out
(t)
C
load
I
dsn
(t)
0
0
( )
( )
( )
( )
ou
DD in
t
out
u t t V
d
d
t
t t
V t
V
V
t
=
= <

=
V
in
(t)
V
out
(t)
C
load
I
dsn
(t)
0
0
(
( ) )
(
(
)
)
DD
D o
i
D
o t
n
ut
u
V t
u t t V
V
d
d
t
t
V
V
t
t
=
= <
=
V
in
(t)
V
out
(t)
C
load
I
dsn
(t)
0
0
( )
( )
( )
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
V
V
u t t V
t t
V t
V
d
dt C
t
I t
=
=
=
<
0
( )
DD t out
ou
ds
t DD t
n
I t V V
V V V
V
t t s
= >
<
V
in
(t)
V
out
(t)
C
load
I
dsn
(t)
0
0
( )
( )
( )
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
V
V
u t t V
t t
V t
V
d
dt C
t
I t
=
=
=
<
( )
0
2
2
0
2
)
)
(
( )
(
DD DD t
DD
out
out
out out D t
n
t
ds
D
I V
t t
V V V V
V V V V V
t
V t
V t
|
|
= >
| |
<
|
\ .
V
in
(t)
V
out
(t)
C
load
I
dsn
(t)
0
0
( )
( )
( )
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
V
V
u t t V
t t
V t
V
d
dt C
t
I t
=
=
=
<
( )
0
2
2
0
2
)
)
(
( )
(
DD DD t
DD
out
out
out out D t
n
t
ds
D
I V
t t
V V V V
V V V V V
t
V t
V t
|
|
= >
| |
<
|
\ .
V
out
(t)
V
in
(t)
t
0
t
V
in
(t)
V
out
(t)
C
load
I
dsn
(t)
Delay Definitions
t
pdr
:

t
pdf
:

t
pd
:

t
r
:

t
f
: fall time
Delay Definitions
t
pdr
: rising propagation delay
From input to rising output crossing V
DD
/2
t
pdf
: falling propagation delay
From input to falling output crossing V
DD
/2
t
pd
: average propagation delay
t
pd
= (t
pdr
+ t
pdf
)/2
t
r
: rise time (aka, transistion time)
From output crossing 0.2 V
DD
to 0.8 V
DD

t
f
: fall time (aka, transistion time)
From output crossing 0.8 V
DD
to 0.2 V
DD
Delay Definitions
t
cdr
: rising contamination delay
From input to rising output crossing V
DD
/2
this is a MINIMUM time
t
cdf
: falling contamination delay
From input to falling output crossing V
DD
/2
this is a MINIMUM time
t
cd
: average contamination delay
t
pd
= (t
cdr
+ t
cdf
)/2
Contamination delays used for race conditions.
Trigger Point
V
DD
/2 is the trigger point for delay measurement
Prop delay measured from 50% Vin to 50% Vout
Can also choose different points
40%/60% points
inverting TPHL - 40% Vin to 60% Vout
noninverting TPHL 60% Vin to 60% Vout
30%/70% points
inverting TPHL - 30% Vin to 70% Vout
noninverting TPHL 70% Vin to 70% Vout
Advantage of 50% is that definition is same for inverting/non-
inverting delays. Disadvantage is that for long transition times,
the 50% trigger point can yield negative delays.
Just be consistent in how delay is measured.
Simulated Inverter Delay
Solving differential equations by hand is too hard
SPICE simulator solves the equations numerically
Uses more accurate I-V models too!
But simulations take time to write
(V)
0.0
0.5
1.0
1.5
2.0
t(s)
0.0 200p 400p 600p 800p 1n
t
pdf
= 66ps t
pdr
= 83ps
V
in
V
out
Delay Estimation
We would like to be able to easily estimate delay
Not as accurate as simulation
But easier to ask What if?
The step response usually looks like a 1
st
order RC
response with a decaying exponential.
Use RC delay models to estimate delay
C = total capacitance on output node
Use effective resistance R
So that t
pd
= RC
Characterize transistors by finding their effective R
Depends on average current as gate switches
RC Delay Models
Use equivalent circuits for MOS transistors
Ideal switch + capacitance and ON resistance
Unit nMOS has resistance R, capacitance C
Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance inversely proportional to width
k g
s
d
g
s
d
kC
kC
kC
R/k
k g
s
d
g
s
d
kC
kC
kC
2R/k
Example: 3-input NAND
Sketch a 3-input NAND with transistor widths
chosen to achieve effective rise and fall resistances
equal to a unit inverter (R).
3
3
2 2 2
3
3-input NAND Caps
Annotate the 3-input NAND gate with gate and
diffusion capacitance.
2 2 2
3
3
3
3-input NAND Caps
2 2 2
3
3
3
3C
3C
3C
3C
2C
2C
2C
2C
2C
2C
3C
3C
3C
2C 2C 2C
3-input NAND Caps
9C
3C
3C
3
3
3
2 2 2
5C
5C
5C
Elmore Delay
ON transistors look like resistors
Pullup or pulldown network modeled as RC ladder
Elmore delay of RC ladder
R
1
R
2
R
3
R
N
C
1
C
2
C
3
C
N
( ) ( )
nodes
1 1 1 2 2 1 2
... ...
pd i to source i
i
N N
t R C
RC R R C R R R C

~
= + + + + + + +

Estimate worst-case rising and falling delay of 2-
input NAND driving h identical gates.
h copies
2
2
2 2
B
A
x
Y
Estimate rising and falling propagation delays of a 2-
h copies
6C
2C
2
2
2 2
4hC
B
A
x
Y
h copies
6C
2C
2
2
2 2
4hC
B
A
x
Y
R
(6+4h)C
Y
pdr
t =
h copies
6C
2C
2
2
2 2
4hC
B
A
x
Y
R
(6+4h)C
Y
( )
6 4
pdr
t h RC = +
h copies
6C
2C
2
2
2 2
4hC
B
A
x
Y
h copies
6C
2C
2
2
2 2
4hC
B
A
x
Y
pdf
t =
(6+4h)C 2C
R/2
R/2
x
Y
h copies
6C
2C
2
2
2 2
4hC
B
A
x
Y
( ) ( ) ( ) ( )
( )
2 2 2
2 6 4
7 4
R R R
pdf
t C h C
h RC
= + + + (

= +
(6+4h)C 2C
R/2
R/2
x
Y
Delay Components
Delay has two parts
Parasitic delay
6 or 7 RC
Independent of load
Effort delay
4h RC
Proportional to load capacitance
Contamination Delay
Best-case (contamination) delay can be substantially
less than propagation delay.
Ex: If both inputs fall simultaneously
6C
2C
2
2
2 2
4hC
B
A
x
Y
R
(6+4h)C
Y
R
( )
3 2
cdr
t h RC = +
7C
3C
3C
3
3
3
2 2 2
3C
2C 2C
3C 3C
Isolated
Contacted
Diffusion
Merged
Uncontacted
Diffusion
Shared
Contacted
Diffusion
Diffusion Capacitance
we assumed contacted diffusion on every s / d.
Good layout minimizes diffusion area
Ex: NAND3 layout shares one diffusion contact
Reduces output capacitance by 2C
Merged uncontacted diffusion might help too
Layout Comparison
Which layout is better?
A
V
DD
GND
B
Y
A
V
DD
GND
B
Y

Introduction To Cmos Vlsi Design: DC & Transient Response

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Introduction To Cmos Vlsi Design: DC & Transient Response

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Introduction to

CMOS VLSI Design 4: DC and Transient Response Slide 53

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