Introduction to

CMOS VLSI
Design

Lecture 8:
Combinational Circuits
David Harris



Harvey Mudd College
Spring 2004
CMOS VLSI Design 8: Combinational Circuits Slide 2
Outline
Bubble Pushing
Compound Gates
Logical Effort Example
Input Ordering
Asymmetric Gates
Skewed Gates
Best P/N ratio
CMOS VLSI Design 8: Combinational Circuits Slide 3
Example 1
module mux(input s, d0, d1,
output y);

assign y = s ? d1 : d0;
endmodule

1) Sketch a design using AND, OR, and NOT gates.
CMOS VLSI Design 8: Combinational Circuits Slide 4
Example 1
module mux(input s, d0, d1,
output y);

assign y = s ? d1 : d0;
endmodule

1) Sketch a design using AND, OR, and NOT gates.
D0
S
D1
S
Y
CMOS VLSI Design 8: Combinational Circuits Slide 5
Example 2
2) Sketch a design using NAND, NOR, and NOT gates.
Assume ~S is available.
CMOS VLSI Design 8: Combinational Circuits Slide 6
Example 2
2) Sketch a design using NAND, NOR, and NOT gates.
Assume ~S is available.
Y
D0
S
D1
S
CMOS VLSI Design 8: Combinational Circuits Slide 7
Bubble Pushing
Start with network of AND / OR gates
Convert to NAND / NOR + inverters
Push bubbles around to simplify logic
Remember DeMorgans Law
Y Y
Y
D
Y
(a) (b)
(c) (d)
CMOS VLSI Design 8: Combinational Circuits Slide 8
Example 3
3) Sketch a design using one compound gate and one
NOT gate. Assume ~S is available.
CMOS VLSI Design 8: Combinational Circuits Slide 9
Example 3
3) Sketch a design using one compound gate and one
NOT gate. Assume ~S is available.
Y
D0
S
D1
S
CMOS VLSI Design 8: Combinational Circuits Slide 10
Compound Gates
Logical Effort of compound gates
A
B
C
D
Y
A
B
C
Y
A
B
C
C
A B
A
B
C
D
A
C
B
D
2
2
1
4
4 4
2
2 2
2
4
4 4
4
g
A
= 6/3
g
B
= 6/3
g
C
= 5/3
p = 7/3
g
A
=
g
B
=
g
C
=
p =
g
D
=
Y A
A Y
g
A
= 3/3
p = 3/3
2
1
Y Y
unit inverter AOI21 AOI22
A
C
D
E
Y
B
Y
B C
A
D
E
A
B
C
D E
g
A
=
g
B
=
g
C
=
g
D
=
2
2 2
2 2
6
6
6 6
3
p =
g
E
=
Complex AOI
Y A B C Y A B C D
Y A B C D E
Y A
CMOS VLSI Design 8: Combinational Circuits Slide 11
Compound Gates
Logical Effort of compound gates
A
B
C
D
Y
A
B
C
Y
A
B
C
C
A B
A
B
C
D
A
C
B
D
2
2
1
4
4 4
2
2 2
2
4
4 4
4
g
A
= 6/3
g
B
= 6/3
g
C
= 5/3
p = 7/3
g
A
= 6/3
g
B
= 6/3
g
C
= 6/3
p = 12/3
g
D
= 6/3
Y A
A Y
g
A
= 3/3
p = 3/3
2
1
Y Y
unit inverter AOI21 AOI22
A
C
D
E
Y
B
Y
B C
A
D
E
A
B
C
D E
g
A
= 5/3
g
B
= 8/3
g
C
= 8/3
g
D
= 8/3
2
2 2
2 2
6
6
6 6
3
p = 16/3
g
E
= 8/3
Complex AOI
Y A B C Y A B C D
Y A B C D E
Y A
CMOS VLSI Design 8: Combinational Circuits Slide 12
Example 4
The multiplexer has a maximum input capacitance of
16 units on each input. It must drive a load of 160
units. Estimate the delay of the NAND and
compound gate designs.
CMOS VLSI Design 8: Combinational Circuits Slide 13
Example 4
The multiplexer has a maximum input capacitance of
16 units on each input. It must drive a load of 160
units. Estimate the delay of the NAND and
compound gate designs.
Y
D0
S
D1
S
Y
D0
S
D1
S
H = 160 / 16 = 10
B = 1
N = 2
CMOS VLSI Design 8: Combinational Circuits Slide 14
NAND Solution
Y
D0
S
D1
S
CMOS VLSI Design 8: Combinational Circuits Slide 15
NAND Solution
Y
D0
S
D1
S
2 2 4
(4/ 3) (4/ 3) 16/ 9
160/ 9

4.2

12.4
N
P
G
F GBH
f F
D Nf P





CMOS VLSI Design 8: Combinational Circuits Slide 16
Compound Solution
Y
D0
S
D1
S
CMOS VLSI Design 8: Combinational Circuits Slide 17
Compound Solution
4 1 5
(6/ 3) (1) 2
20

4.5

14
N
P
G
F GBH
f F
D Nf P





Y
D0
S
D1
S
CMOS VLSI Design 8: Combinational Circuits Slide 18
Example 5
Annotate your designs with transistor sizes that
achieve this delay.
Y Y
CMOS VLSI Design 8: Combinational Circuits Slide 19
Example 5
Annotate your designs with transistor sizes that
achieve this delay.
6
6 6
6
10
10
Y
24
12
10
10
8
8
8 8
8
8
8 8
25
25
25 25
Y
16
16 160 * (4/3) / 4.2 = 50 160 * 1 / 4.5 = 36
CMOS VLSI Design 8: Combinational Circuits Slide 20
Input Order
Our parasitic delay model was too simple
Calculate parasitic delay for Y falling
If A arrives latest?
If B arrives latest?
6C
2C
2
2
2 2
B
A
x
Y
CMOS VLSI Design 8: Combinational Circuits Slide 21
Input Order
Our parasitic delay model was too simple
Calculate parasitic delay for Y falling
If A arrives latest? 2
If B arrives latest? 2.33
6C
2C
2
2
2 2
B
A
x
Y
CMOS VLSI Design 8: Combinational Circuits Slide 22
Inner & Outer Inputs
Outer input is closest to rail (B)
Inner input is closest to output (A)

If input arrival time is known
Connect latest input to inner terminal
2
2
2 2
B
A
Y
CMOS VLSI Design 8: Combinational Circuits Slide 23
Asymmetric Gates
Asymmetric gates favor one input over another
Ex: suppose input A of a NAND gate is most critical
Use smaller transistor on A (less capacitance)
Boost size of noncritical input
So total resistance is same
g
A
=
g
B
=
g
total
= g
A
+ g
B
=
Asymmetric gate approaches g = 1 on critical input
But total logical effort goes up
A
reset
Y
4/3
2
reset
A
Y
CMOS VLSI Design 8: Combinational Circuits Slide 24
Asymmetric Gates
Asymmetric gates favor one input over another
Ex: suppose input A of a NAND gate is most critical
Use smaller transistor on A (less capacitance)
Boost size of noncritical input
So total resistance is same
g
A
= 10/9
g
B
= 2
g
total
= g
A
+ g
B
= 28/9
Asymmetric gate approaches g = 1 on critical input
But total logical effort goes up
A
reset
Y
4
4/3
2 2
reset
A
Y
CMOS VLSI Design 8: Combinational Circuits Slide 25
Symmetric Gates
Inputs can be made perfectly symmetric
A
B
Y
2
1
1
2
1
1
CMOS VLSI Design 8: Combinational Circuits Slide 26
Skewed Gates
Skewed gates favor one edge over another
Ex: suppose rising output of inverter is most critical
Downsize noncritical nMOS transistor



Calculate logical effort by comparing to unskewed
inverter with same effective resistance on that edge.
g
u
=
g
d
=
1/2
2
A Y
1
2
A Y
1/2
1
A Y
HI-skew
inverter
unskewed inverter
(equal rise resistance)
unskewed inverter
(equal fall resistance)
CMOS VLSI Design 8: Combinational Circuits Slide 27
Skewed Gates
Skewed gates favor one edge over another
Ex: suppose rising output of inverter is most critical
Downsize noncritical nMOS transistor



Calculate logical effort by comparing to unskewed
inverter with same effective resistance on that edge.
g
u
= 2.5 / 3 = 5/6
g
d
= 2.5 / 1.5 = 5/3
1/2
2
A Y
1
2
A Y
1/2
1
A Y
HI-skew
inverter
unskewed inverter
(equal rise resistance)
unskewed inverter
(equal fall resistance)
CMOS VLSI Design 8: Combinational Circuits Slide 28
HI- and LO-Skew
Def: Logical effort of a skewed gate for a particular
transition is the ratio of the input capacitance of that
gate to the input capacitance of an unskewed
inverter delivering the same output current for the
same transition.

Skewed gates reduce size of noncritical transistors
HI-skew gates favor rising output (small nMOS)
LO-skew gates favor falling output (small pMOS)
Logical effort is smaller for favored direction
But larger for the other direction
CMOS VLSI Design 8: Combinational Circuits Slide 29
Catalog of Skewed Gates
1/2
2
A Y
Inverter
B
A
Y
B
A
NAND2 NOR2
HI-skew
LO-skew
1
1
A Y
B
A
Y
B
A
g
u
= 5/6
g
d
= 5/3
g
avg
= 5/4
g
u
= 4/3
g
d
= 2/3
g
avg
= 1
g
u
=
g
d
=
g
avg
=
g
u
=
g
d
=
g
avg
=
g
u
=
g
d
=
g
avg
=
g
u
=
g
d
=
g
avg
=
Y
Y
1
2
A Y
2
2
2 2
B
A
Y
B
A
1 1
4
4
unskewed
g
u
= 1
g
d
= 1
g
avg
= 1
g
u
= 4/3
g
d
= 4/3
g
avg
= 4/3
g
u
= 5/3
g
d
= 5/3
g
avg
= 5/3
Y
CMOS VLSI Design 8: Combinational Circuits Slide 30
Catalog of Skewed Gates
1/2
2
A Y
Inverter
1
1
2 2
B
A
Y
B
A
NAND2 NOR2
1/2 1/2
4
4
HI-skew
LO-skew
1
1
A Y
2
2
1 1
B
A
Y
B
A
1 1
2
2
g
u
= 5/6
g
d
= 5/3
g
avg
= 5/4
g
u
= 4/3
g
d
= 2/3
g
avg
= 1
g
u
=
g
d
=
g
avg
=
g
u
=
g
d
=
g
avg
=
g
u
=
g
d
=
g
avg
=
g
u
=
g
d
=
g
avg
=
Y
Y
1
2
A Y
2
2
2 2
B
A
Y
B
A
1 1
4
4
unskewed
g
u
= 1
g
d
= 1
g
avg
= 1
g
u
= 4/3
g
d
= 4/3
g
avg
= 4/3
g
u
= 5/3
g
d
= 5/3
g
avg
= 5/3
Y
CMOS VLSI Design 8: Combinational Circuits Slide 31
Catalog of Skewed Gates
1/2
2
A Y
Inverter
1
1
2 2
B
A
Y
B
A
NAND2 NOR2
1/2 1/2
4
4
HI-skew
LO-skew
1
1
A Y
2
2
1 1
B
A
Y
B
A
1 1
2
2
g
u
= 5/6
g
d
= 5/3
g
avg
= 5/4
g
u
= 4/3
g
d
= 2/3
g
avg
= 1
g
u
= 1
g
d
= 2
g
avg
= 3/2
g
u
= 2
g
d
= 1
g
avg
= 3/2
g
u
= 3/2
g
d
= 3
g
avg
= 9/4
g
u
= 2
g
d
= 1
g
avg
= 3/2
Y
Y
1
2
A Y
2
2
2 2
B
A
Y
B
A
1 1
4
4
unskewed
g
u
= 1
g
d
= 1
g
avg
= 1
g
u
= 4/3
g
d
= 4/3
g
avg
= 4/3
g
u
= 5/3
g
d
= 5/3
g
avg
= 5/3
Y
CMOS VLSI Design 8: Combinational Circuits Slide 32
Asymmetric Skew
Combine asymmetric and skewed gates
Downsize noncritical transistor on unimportant
input
Reduces parasitic delay for critical input
A
reset
Y
4
4/3
2 1
reset
A
Y
CMOS VLSI Design 8: Combinational Circuits Slide 33
Best P/N Ratio
We have selected P/N ratio for unit rise and fall
resistance (m = 2-3 for an inverter).
Alternative: choose ratio for least average delay
Ex: inverter
Delay driving identical inverter
t
pdf
=
t
pdr
=
t
pd
=
Differentiate t
pd
w.r.t. P
Least delay for P =
1
P
A
CMOS VLSI Design 8: Combinational Circuits Slide 34
Best P/N Ratio
We have selected P/N ratio for unit rise and fall
resistance (m = 2-3 for an inverter).
Alternative: choose ratio for least average delay
Ex: inverter
Delay driving identical inverter
t
pdf
= (P+1)
t
pdr
= (P+1)(m/P)
t
pd
= (P+1)(1+m/P)/2 = (P + 1 + m + m/P)/2
Differentiate t
pd
w.r.t. P
Least delay for P =
1
P
A
m
CMOS VLSI Design 8: Combinational Circuits Slide 35
P/N Ratios
In general, best P/N ratio is sqrt of equal delay ratio.
Only improves average delay slightly for inverters
But significantly decreases area and power
Inverter NAND2 NOR2
1
1.414
A Y
2
2
2 2
B
A
Y
B
A
1 1
2
2
fastest
P/N ratio
g
u
=
g
d
=
g
avg
=
g
u
=
g
d
=
g
avg
=
g
u
=
g
d
=
g
avg
=
Y
CMOS VLSI Design 8: Combinational Circuits Slide 36
P/N Ratios
In general, best P/N ratio is sqrt of that giving equal
delay.
Only improves average delay slightly for inverters
But significantly decreases area and power
Inverter NAND2 NOR2
1
1.414
A Y
2
2
2 2
B
A
Y
B
A
1 1
2
2
fastest
P/N ratio
g
u
= 1.15
g
d
= 0.81
g
avg
= 0.98
g
u
= 4/3
g
d
= 4/3
g
avg
= 4/3
g
u
= 2
g
d
= 1
g
avg
= 3/2
Y
CMOS VLSI Design 8: Combinational Circuits Slide 37
Observations
For speed:
NAND vs. NOR
Many simple stages vs. fewer high fan-in stages
Latest-arriving input
For area and power:
Many simple stages vs. fewer high fan-in stages