Agenda

Power Dissipation in CMOS

Low Power Design Challenges


Introduction to UPF


UPF & CPF

Advantages of UPF
F.I Vs P.I
Low Power Design and Verification Flow
Basic Terminologies

Power Management Architecture & Cells


Power Management Techniques


Implementation of UPF

Power Dissipation in CMOS
Low Power Design Challenges
Basic Idea
What is UPF?
Unified Power Format

UPF provides the ability for electronic systems to be designed with
power as a key consideration early in the process.

Why UPF?
No existing HDL adequately supports the specification of power
distribution and management.
Vendor-specific formats are non-portable and create opportunities
for bugs via inconsistent specifications.
The Unified Power Format (UPF)
Working Group Entity Members
Fast Response to Industry Need
UPF & CPF :-
These are the two power-formats that are recognized through-out
the industry which specifies power-gating considerations for a design.

Low power Cells which are specified in the UPF or CPF are inserted
separately in the netlist.

Power Compilers (Cadence RC who works on CPF ) and (Synopsys DC
which works on UPF) than reads the power intent and insert the low
power cells in the netlist. Thus at GLS it can be checked that power-
domains are following the power-up and power-down sequence
correctly.

UPF IEEE standard and 1.0, 2.0 are currently available.
CPF Maintained by Si2 group and versions 1.0, 1.0e, 1.1 and 2.0 are
currently available.
Advantages of UPF:-
>The UPF file is the input to several tools (e.g., simulation,
synthesis, formal verification, and place-and-route tools).

>Synthesis tools can read the RTL/UPF design input files and
produce a netlist.

>The UPF file may be reused without change later in the tool flow.

>A UPF specification can be included with the other deliverables of
intellectual-property (IP) blocks and reused along with the other
delivered IP files.

>The same standard can be used in a multi-vendor tool flow.

Functional Intent Vs Power Intent
Low Power Design and Verification
Few Terminologies :-
Operating corner

Power Domain

Power mode

Power Switch Rule

State Retention Rule

Power Switch Cell

Power Management Architecture:-
Power States and Transitions

Isolation and Level Shifting

State Retention
Isolation Cells :-
Isolation cells are typically used to protect logic that is powered on
from logic that is powered off.

Used to prevent unknown values in unpowered logic from propagating
into live logic

Can also be used to prevent leakage current from live logic from
improperly powering unpowered logic.
Level Shifters :-
Changes the voltage from one discrete value to another discrete value.

A 1b1 driven by 1.0 logic may be too much for 0.7 logic and likewise a
1b1 from 0.7 logic may not translate into 1b1 for 1.0 logic.

A Level Shifter changes a 0.7V 1b1 so you are propagating valid digital
values through the circuit.
State Retention :-
A Sequential element that can retain its value despite being powered
off.

Useful to recover the last known state of the design when power was
removed.

Reduces the amount of time needed reset a design to a specific state to
continue operation.
Power Management Techniques:-
Power Gating

Multi-Voltage

Dynamic voltage and frequency scaling
Power Gating:-
Power reduction technique to reduce leakage power by shutting-
off , or powering down unnecessary logic.

Can be enabled by power switch or MTCMOS cells.
Sleep Transistor used in Power Gating
Multi Voltage:-
Power Saving Technique to operate different logic blocks at
different voltages.
Bias Voltage:-
Used to change the threshold value of the cell to improve the
leakage characteristics of the cell.
Dynamic Voltage and Frequency Scaling:-
Power saving technique to change the voltage/or clock frequency
while the chip is running .
Results
Multi-Voltage Special Cells Requirement