SystemVerilog_1

Unit 1 Verification Guidelines

Unit 2 Object Oriented Programming
Unit 3 Introduction to SystemVerilog
Unit 4 Enhancements in SystemVerilog
Unit 5 Conclusion
Unit 1 Verification Guidelines
Unit 2 Object Oriented Programming
Unit 3 Introduction to SystemVerilog
Unit 4 Enhancements in SystemVerilog
Unit 4 Conclusion
Verification Guidelines
A process of investigating a design and demonstrating it
to be accurate to specification.

A process which runs simultaneous to design creation
process.

Verification as part of our daily routine:
Commutation.
Tasting a cuisine.
We even verify our thoughts.

An Engineers job
Interpret the design specification
Exercise tests on RTL
Making sure the tests signify the interpretation accurately
Importance:
Finding bugs in design.
Authenticate the design to be accurate to its specification.
To make sure the design and the verification is robust.

A generic process:
Start with verification plan.
List out all features of design that needs to be exercised
Develop an verification environment which includes a Testbench.

Testbench?
A virtual environment which generates stimulus and verifies the
correctness of a design.

DUT
A Testbench connects with DUT and checks
correctness of the DUT
Basic functionality:
Generate data to DUT
Apply data to DUT
Receive the response from the DUT
Check for correctness
Testbench
A Testbench consists of different components called Bus Functional
Modules(BFMs)
BFMs are divided into layers on the basis of concept of layered testbench
Generator
Driver
DUT
Scoreboard
Receiver
Checker
Transactor
interface
C
Functional
Command
Signal
Scenario
Features of SV:
Constrained Random Generation
SystemVerilog Assertions
Interfaces and Clocking blocks
Functional and Code Coverage
Threads and Interprocess Communication.

Methodologies Based on SystemVerilog
VMM(Verification Methodology Manual)
OVM(Open Verification Methodology)
UVM(Universal Verification Methodology)
Importance:
Layered testbench using Bus functional modules.
Common testbench for all tests.
Test specific code kept separate from testbench.

Directed versus Random testing
Random test
Directed test
Time
C
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r
a
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100%
COVERAGE CONVERGENCE
Test progress with and without feedback
A random test evolves using feedback.
Functional coverage elevates with feedback.(Coverage Driven Verification)
A 100% coverage declares a testbench to be robust

Time
C
o
v
e
r
a
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100%
Without feedback
With feedback
Checker Generator
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Driver
DUT
Transactor
Scoreboard
Receiver
C
Interface
Environment
Test
F
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C
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Build phase
Configure generator
Build Environment by connecting components
Reset the design
Configure the DUT

Run phase
Start environment
Run the test

Wrap-up phase
Wait until final transaction is exercised on DUT
Generate report

Tip: Make the environment generic for better re-usability
DUT
Generator Checker Generator
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Driver
DUT
Transactor
Scoreboard
Receiver
C
Interface
Environment: BUILD PHASE
Configure generator
Build
Reset DUT, Configure DUT
Test
Checker Generator
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Driver
DUT
Transactor
Scoreboard
Receiver
C
Interface
Test
F
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io
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al
C
o
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Environment: RUN PHASE
Start environment
Run the test

Unit 1 Verification Guidelines
Unit 2 Object Oriented Programming
Unit 3 Introduction to SystemVerilog
Unit 4 Enhancements in SystemVerilog
Unit 5 Conclusion
Object Oriented Programming
Encapsulation
Classes
Polymorphism
Inheritance
Introduction to OOP
OOP
Basic OOP
OOP breaks a testbench into blocks that work together to
accomplish the verification goal
Why OOP?
Highly abstract system level modeling
Classes are intended for verification
Classes are easily reused and extended
Data security
Classes are dynamic in nature
Easy debugging, one class at a time
OOP cont..
Why
SystemVerilog?

Why Not C++?
Why not C++?
C++ System Verilog
Superset of Verilog
RTL/Verification language
Assertion language
Constraint language
Code coverage language
No relation to
verilog
Interface is required
to interact with Verilog
Comparison
A class encapsulation is a process of hiding all internal details
of an object from out side world.

Encapsulation is the ability to hide data and methods from out
side world and only expose data and methods that are required.
DATA ENCAPSULATION
Class Encapsulation

Polymorphism refers to the ability to assume different
forms. In OOP, it indicates a languages ability to handle
objects differently based on their runtime type.

When objects communicate with one another, we say that
they send and receive messages.

The sending object only needs to be aware that the
receiving object can perform a particular behaviour.

Polymorphism





class A ;
task disp ();
$display(" This is class A ");
endtask
endclass

class EA extends A ;
task disp ();
$display(" This is Extended class A ");
endtask
endclass

program main ;
EA my_ea;
A my_a;

initial
begin
my_a = new();
my_a.disp();

my_ea = new();
my_a = my_ea;
my_a.disp();
end
endprogram
RESULTS
This is class A
This is class A
The advantage of polymorphism is that the sender of a
message doesnt need to know which class the receiver is a
member of. It can be any arbitrary class.
Definition (Inheritance) Inheritance is the mechanism
which allows a class A to inherit properties of a class B.

We say ``A inherits from B''.

Objects of class A thus have access to attributes and
methods of class B without the need to redefine them.

The following definition defines two terms with which we
are able to refer to participating classes when they use
inheritance.
INHERITANCE
The idea of inheritance is simple but powerful:

When you want to create a new class and there is already a class
that includes some of the code that you want, you can derive your
new class from the existing class.

In doing this, you can reuse the fields and methods of the existing
class without having to write (and debug!) them yourself.

Inheritance cont..
Organized into groups with similar characteristics
They are said to be related by a common characteristic
Object-Oriented programming seeks to provide mechanisms
for modelling these relationships
Objects
It is a pointer to an object.

An oop handle is like the address of the object but is stored in a
pointer that only refer to one type.



Ex:Class Transaction;
logic addr,data;
Endclass

Initial begin
Transaction tr
tr=new();
end
Variables..
Class Transaction
Variables
Memory
Handle
tr
What is Handle?
Unit 1 Verification Guidelines
Unit 2 Object Oriented Programming
Unit 3 Introduction to SystemVerilog
Unit 4 Enhancements in SystemVerilog
Unit 5 Conclusion
An Introduction to SystemVerilog



A Hardware Verification Language(HVL).
SystemVerilog is an extension of IEEE 1364 Verilog-2001 standard.
It has features derived from Verilog, C and C++.

modules
Parameters
Function/tasks
Always @
Assign
Fork-join
Wire , reg
Packed arrays
Wait # @


C ports
Local Param
Generate
$value$plusargs
Multidimensional
array
Signed types
Automatic
Logic
Shortreal
Assertions
Program blocks
Interface
Clocking blocks
Interprocess
communication
Coverage
Constrained-
random stimulus
Verilog-1995
Verilog-2001
SystemVerilog
C, C++

Assertions
OOP support
Constrained Randomization
New data types ie,logic
Coverage support
Easy c model integration
SystemVerilog

Unit 1 Verification Guidelines
Unit 2 Object Oriented Programming
Unit 3 Introduction to SystemVerilog
Unit 4 Enhancements in SystemVerilog
Unit 5 Conclusion
Enhancements in SystemVerilog


SystemVerilog adds abstract data types
2-state types: int, shortint, longint, byte, bit
Special types: void, shortreal
Allows modeling at a C-language level of abstraction
More intuitive data types for system-level modeling

Verilog has hardware-centric net data types
Intended to represent real connections in silicon
Models detailed hardware behavior using 4-state logic, strength
levels and wired logic resolution
Most hardware can be modeled using abstract 2-state logic






The SystemVerilog 2-state data types (bit, byte, int)
Allow mixing 2-state and 4-state in the same design
Give deterministic results all tools are using the same data type
semantics
Verilog uses 4-state logic
Most hardware can be modeled with 2-state logic
Synthesis uses 2-state logic (except tri-state outputs)




SystemVerilog adds enumerated types, using enum
Similar syntax as in C
Special methods are provided to increment to the next
value in the list, go to the first item in the list, etc

Verilog does not have enumerated types
All signals must be declared
All signals must be initialized to a value

enum{START, WAIT, LOAD, READY, GO, ERROR}states;

parameter START = 3b000;
parameter WAIT = 3b001;
parameter LOAD = 3b010;
parameter READY = 3b011;
parameter GO = 3b100;
parameter ERROR = 3b101;
SystemVerilog adds user-defined types
Uses the typedef keyword, as in C



Verilog does not have user-defined data types
Only the built-in data types can be used as wire, reg,
integer, real.
Typedef int unsigned uint;
Uint a, b; //two unsigned integers
Typedef enum {FALSE=1b0, TRUE=1b1} boolean;
boolean ready; //signal ready can be FALSE or TRUE
SystemVerilog adds structures and unions.
Uses a syntax similar to C
Can be given a type name, using typedef
Structures can be assigned a value as a whole





Verilog does not have a convenient way to bundle several
signals together.
Must use modules as pseudo-structures
typedef union {
int i; //2state
integerj;//4-state
}data_word;
struct
{bit [7:0] opcode;
bit [23:0] addr;
data_word data;}instruction; //named structure
type
IR = {5, 200, 0}; //fill the structure
SystemVerilog adds:
++and --increment and decrement operators
+=, -=, *=, /=, %=, &=, ^=, |=, <<=, >>=, <<<=,
>>>=assignment operators



Verilog does not have Cs increment and decrement operators


for (i = 0; i <= 255; i++)
...
for (i = 0; i <= 255; i = i + 1)...
bit b; //2 state ,single bit
bit [31:0] b32; //2 state, 32 bit unsigned integer
int unsigned ui; //2 state ,32
int I; // 2 state ,32 bit signed integer
Byte b8 ; // 2state 8bit signed integer
shortint s; //2state 16 bit signed integer
longint l ; // 2state 64 bit signed integer
Integer i4 //4state 32 bit signed integer
time t ; // 4state 64 bit unsigned integer
real r ; // 2state double precision floating point

Declaring fixed size array
int ary [0:15]





You can create multidimensional array by specifying the
dimension s after the variable name.
ary[0]
ary[13]
Many system verilog simulator store each element on 32 bit
word boundary.
A byte ,shortint and int are stored in a single word.
Longint is stored in two words.
An unpacked array stores the value in the lower portion of the
words where the upper bits are unused.
Syntax of unpacked array
bit [7:0] un_pck [3] ;

Unpacked array storage

0-7 data
0-7 data
0-7 data
Unused space
Unused space
Unused space
For data types, you may need to access the entire value.
A systemverilog packed array is treated as single valure.
It is specified in the [msb:lsb] format, not in size.

bit [3:0][7:0] bytes;
bytes =32h0123_4567;


What if u want something really large array?
If u allocate and initialize gigabyte of array, may be wasteful
for some time.
For ex: during typical test, a processor may reaches few
hundreds of locations containing code and data.
So allocating and initializing gigabyte of array is wasteful.
SV offers associative array.


Associative array stores entries in a sparse matrix.
This means, while you can address vary very large address
very large address space, SystemVerilog only allocate memory
for an element when you write in to it.

SV introduces a new data type called Queue.
It allow you to add or remove elements any where in the
queue.
Queue is declared with word subscript containing a $ sign:[$].










int j=1,
q2[$]={3,4};
q[$]={0,2,5};
initial begin
q.insert(1,j); // insert 1
before 2
q.insert(3,q2); // insert queue
in q
end

Variable-sized Array: data_type name [$]
Use:







Synthesizable if maximum size is known
q[$:25] // maximum size is 25
array syntax and operators
int q[$] = { 2, 4, 8 }; int e, pos, p[$];
e = q[0]; // read the first (leftmost) item
e = q[$]; // read the last (rightmost) item
q = { q, 6 }; // append: insert 6 at the end
q = { e, q }; // insert e at the beginning
q = q[1:$]; // delete the first (leftmost) item
q = q[1:$-1]; // delete the first and last items

Unit 1 Verification Guidelines
Unit 2 Object Oriented Programming
Unit 3 Introduction to SystemVerilog
Unit 4 Enhancements in SystemVerilog
Unit 5 Conclusion
Directed tests only test one feature at a time and cannot create
the complex stimulus and configurations that the device would
be subjected to in the real world
To cover wildest possible range of stimulus we need to go for
constrained random stimulus generation which is combined with
functional coverage
OOP techniques in SystemVerilog allows to change the behavior
of the testbench without changing the whole code of the
testbench
SystemVerilog provides many new data types which are not
there in the verilog to create high level testbench
SystemVerilog provides dynamic arrays to set the size during
the simulation.