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PROFESSIONAL
UNIVERSITY
I ntroduction about VLSI :
Very-large-scale integration (VLSI) is the process of creating
an integrated circuit by combining thousands of transistors into a
single chip.
Before the introduction of VLSI technology most ICs had a limited set
of functions they could perform.
An electronic circuit might consist of a CPU, ROM, RAM and other
logic. VLSI IC makers add all of these into one chip.
IC can be designed in two ways:
Digital
Analog

SOFTWARE FOR VLSI :
Xilink ,Cadence Tool,FPGA
Cadence Design System:
Cadence Design Systems is an American electronic design automation (EDA) software and
engineering services company, founded in 1988.The company produces software and hardware
for designing integrated circuits, systems on chip and printed circuit boards.
Tools:
NCSIM: Tool for simulation and functional verification of RTL including Verilog, VHDL based
models. It is a tool used for Digital design.
Virtuoso: Tools for designing full-custom integrated circuits includes behavioral modeling circuit
simulation, custom layout, physical verification, extraction. Tool used for analog design.
NCSI M:
It is a tools from Cadence Design Systems related to the design and verification
of ASICs, SoCs, and FPGAs.
Initialization commands:
cd /cad
ls
cd Cadence_db
csh
source cshrc1
cd Cadence_digital_labs:
nclaunch
RTL(ENCOUNTER):

Register-transfer level (RTL) is a design abstraction which models a synchronous digital
circuit in terms of the flow of digital signals (data) between hardware registers, and the logical
operations performed on those signals. Register-transfer-level abstraction is used in hardware
description languages (HDLs) like Verilog and VHDL to create high-level representations of a
circuit, from which lower-level representations and ultimately actual wiring can be derived.

Mini Project based on Adders

ADDERS:
The system which is used for addition of binary bits i.e., addition of 0s &
1s in digital electronics is called adders.

Addition of two bits in digital will be:
0+0=0
0+1=1
1+0=1
1+1=10 [=> carry 1 &sum 0]

Ripple Carry Adder:
The adder which is used for addition of more than three bits is called ripple carry adder.
It consist of fulladder connected in cascade form such that carry output of each adder circuit
is connected to carry input of next higher order full adder circuit
Block diagram:


Programming code in:
module ripplecary(a,b,s,cout);
input [5:0]a,b;
output [5:0]s;
output cout;
wire [4:0]e;
wire c;
assign c=0;
fulladder a1(s[0],e[0],a[0],b[0],c);
fulladder a2(s[1],e[1],a[1],b[1],e[0]);
fulladder a3(s[2],e[2],a[2],b[2],e[1]);
fulladder a4(s[3],e[3],a[3],b[3],e[2]);
fulladder a5(s[4],e[4],a[4],b[4],e[3]);
fulladder a6(s[5],cout,a[5],b[5],e[4]);
endmodule



module fulladder(s,e,a,b,c);
input a,b,c;
output s,e;
wire k,l,m;
xor b1(s,a,b,c);
and b2(k,a,b);
and b3(l,b,c);
and b4(m,c,a);
or b5(e,k,l,m);
endmodule
RTL Analysis:

Area and Worstpath:
Carry Save Adder:
A carry-save adder is a type of digital adder, used in computer microarchitecture to compute
the sum of three or more n-bit numbers in binary. It differs from other digital adders in that it
outputs two numbers of the same dimensions as the inputs, one which is a sequence of partial
sum bits and another which is a sequence of carry bits.
Block Diagram:

Programming Code:
module carrysave(a,b,c,d,s,cout);
input [5:0]a,b,c,d;
output [6:0]s;
output cout;
wire[5:0]e,f,g,h;
wire[4:0]j;
fulladder a1(e[0],f[0],a[0],b[0],c[0]);
fulladder a2(e[1],f[1],a[1],b[1],c[1]);
fulladder a3(e[2],f[2],a[2],b[2],c[2]);
fulladder a4(e[3],f[3],a[3],b[3],c[3]);
fulladder a5(e[4],f[4],a[4],b[4],c[4]);
fulladder a6(e[5],f[5],a[5],b[5],c[5]);
halfadder a7(g[0],h[0],d[0],e[0]);
fulladder a8(g[1],h[1],f[0],d[1],e[1]);
fulladder a9(g[2],h[2],f[1],d[2],e[2]);
fulladder a10(g[3],h[3],f[2],d[3],e[3]);
fulladder a11(g[4],h[4],f[3],d[4],e[4]);
fulladder a12(g[5],h[5],f[4],d[5],e[5]);
halfadder a13(s[1],j[0],h[0],g[1]);
fulladder a14(s[2],j[1],j[0],h[1],g[2]);
fulladder a15(s[3],j[2],j[1],h[2],g[3]);
fulladder a16(s[4],j[3],j[2],h[3],g[4]);
fulladder a17(s[5],j[4],j[3],h[4],g[5]);
fulladder a18(s[6],cout,j[4],h[5],f[5]);
assign s[0]=g[0];
endmodule
module fulladder(e,f,a,b,c);
input a,b,c;
output e,f;
wire k,l,m;
xor b1(e,a,b,c);
and b3(k,a,b);
and b4(l,b,c);
and b5(m,c,a);
or b6(f,k,l,m);
endmodule
module halfadder(s,j,a,b);
input a,b;
output s,j;
xor b7(s,a,b);
and b8(j,a,b);
endmodule
RTL Analysis:
Area and Worstpath:
Carry Select Adder:
Block Diagram:

Programming Code:
module carryselect(a,b,c,e,cout);
input [5:0]a,b;
input c;
output cout;
output [5:0]e;
wire [5:0]g,f,s,m;
wire c1,c2;
assign c1=0;
assign c2=1;
fulladder b1(s[0],g[0],a[0],b[0],c1);
fulladder b2(s[1],g[1],a[1],b[1],g[0]);
fulladder b3(s[2],g[2],a[2],b[2],g[1]);
fulladder b4(s[3],g[3],a[3],b[3],g[2]);
fulladder b5(s[4],g[4],a[4],b[4],g[3]);
fulladder b6(s[5],g[5],a[5],b[5],g[4]);
fulladder b7(m[0],f[0],a[0],b[0],c2);
fulladder b8(m[1],f[1],a[1],b[1],f[0]);
fulladder b9(m[2],f[2],a[2],b[2],f[1]);
fulladder b10(m[3],f[3],a[3],b[3],f[2]);
fulladder b11(m[4],f[4],a[4],b[4],f[3]);
fulladder b12(m[5],f[5],a[5],b[5],f[4]);
mux a3(e[0],s[0],m[0],c);
mux a4(e[1],s[1],m[1],c);
mux a5(e[2],s[2],m[2],c);
mux a6(e[3],s[3],m[3],c);
mux a7(e[4],s[4],m[4],c);
mux a8(e[5],s[5],m[5],c);
mux a9(cout,g[5],f[5],c);
endmodule
module mux(e,s,m,c);
input s,m,c;
output e;
assign e=c?m:s;
endmodule
module fulladder(s,g,a,b,c);
input a,b,c;
output s,g;
wire k,l,m;
xor x1(s,a,b,c);
and x2(k,a,b);
and x3(l,b,c);
and x4(m,c,a);
or x5(g,k,l,m);
endmodule
RTL Analysis:
ADDER AREA NET POWER
Ripple carry adder 98.78 96.55 percent
Carry Save adder 303.41 92.91 percent
Carry Select adder 239.20 93.81 percent
WALLACE TREE
WALLACE TREE

WALLACE TREE


Learning Outcome:
By using Cadence tool such that Ncsim for digital
We can calculate the area, power used by the system and also logically
verification.