http://hello- engineers.blogspot.com/ August 28, 2014 204424 Digital Design Automation 2 Acknowledgement This lecture note has been summarized from lecture note on Introduction to VLSI Design, VLSI Circuit Design all over the world. I cant remember where those slide come from. However, Id like to thank all professors who create such a good work on those lecture notes. Without those lectures, this slide cant be finished. August 28, 2014 204424 Digital Design Automation 3 Todays Topics Course overview Objectives Roadmap for the Semester Administrative Details VLSI Overview Transistor Structure Static CMOS Logic Design Methods & Design Styles VLSI Trends August 28, 2014 204424 Digital Design Automation 4 Course Objectives (1/3) Students should be able to VLSI Circuit Analysis: Understand MOS transistor operation, design eqns. Understand parasitics & perform simple calculations Understand static & dynamic CMOS logic Estimate delay of CMOS gates, networks, & long wires Estimate power consumption Understand design and operation of latches & flip/flops
August 28, 2014 204424 Digital Design Automation 5 Course Objectives (2/3) CMOS Processing and Layout Understand the VLSI manufacturing process. Have an appreciation of current trends in VLSI manufacturing. Understand layout design rules. Design and analyze layouts for simple digital CMOS circuits Design and analyze hierarchical circuit layouts. Understand ASIC Layout styles. August 28, 2014 204424 Digital Design Automation 6 Course Objectives (3/3) VLSI System Design Understand register-transfer level design. Design simple combinational and sequential logic circuits using using a Hardware Description Language (HDL). Design small to medium circuits consisting of multiple components such as a controller and datapath using a HDL. Understand the design flows used in industrial IC design. Design a small standard-cell chip in its entirety using a variety of CAD tools and check it for correct operation.
August 28, 2014 204424 Digital Design Automation 7 Roadmap for the term: major topics VLSI Overview CMOS Processing & Fabrication Components: Transistors, Wires, & Parasitics Design Rules & Layout Combinational Circuit Design & Layout Sequential Circuit Design & Layout Standard-Cell Design with CAD Tools & Verilog Mixed Signal Concerns: D/A, A/D Conversion Design Project: Complete Chip August 28, 2014 204424 Digital Design Automation 8 VLSI Overview Why Make IC IC Evolution Common technologies CMOS Transistors & Logic Gates Structure Switch-Level Transistor Model Basic gates The VLSI Design Process Levels of Abstraction Design steps Design styles VLSI Trends August 28, 2014 204424 Digital Design Automation 9 Why Make ICs Integration improves size speed power Integration reduce manufacturing costs (almost) no manual assembly August 28, 2014 204424 Digital Design Automation 10 IC Evolution (1/3) SSI Small Scale Integration (early 1970s) contained 1 10 logic gates MSI Medium Scale Integration logic functions, counters LSI Large Scale Integration first microprocessors on the chip VLSI Very Large Scale Integration now offers 64-bit microprocessors, complete with cache memory (L1 and often L2), floating-point arithmetic unit(s), etc. August 28, 2014 204424 Digital Design Automation 11 IC Evolution (2/3) Bipolar technology TTL (transistor-transistor logic) ECL (emitter-coupled logic) MOS (Metal-oxide-silicon) although invented before bipolar transistor, was initially difficult to manufacture nMOS (n-channel MOS) technology developed in 1970s required fewer masking steps, was denser, and consumed less power than equivalent bipolar ICs => an MOS IC was cheaper than a bipolar IC and led to investment and growth of the MOS IC market. August 28, 2014 204424 Digital Design Automation 12 IC Evolution (3/3) aluminum gates for replaced by polysilicon by early 1980 CMOS (Complementary MOS): n-channel and p- channel MOS transistors => lower power consumption, simplified fabrication process Bi-CMOS - hybrid Bipolar, CMOS (for high speed) GaAs - Gallium Arsenide (for high speed) Si-Ge - Silicon Germanium (for RF) August 28, 2014 204424 Digital Design Automation 13 Silicon Manufacturing Alternatives Standard Components Application Specific ICs Fixed Application Application by Programming Semi Custom Silicon Compilation Full Custom Logic Families Hardware Programming (MASK) Software Programming TTL CMOS PLA ROM Microprocessor EPROM,EEPROM PLD August 28, 2014 204424 Digital Design Automation 14 VLSI Technology - CMOS Transistors Key feature: transistor length L 2002: L=130nm 2003: L=90nm 2005: L=65nm? August 28, 2014 204424 Digital Design Automation 15 Transistor Switch Model NFET or n transistor on when gate H "good" switch for logic L "poor" switch for logic H "pull-down" device PFET or p transistor on when gate L "good" switch for logic H "poor" switch for logic L "pull-up" device August 28, 2014 204424 Digital Design Automation 16 CMOS Logic Design Complementary transistor networks Pullup: p transistors Pulldown - n transistors VDD Out Gnd VDD Out Gnd Pullup Network (p-transistors) Pulldown Network (n-transistors) In Inputs Inverter August 28, 2014 204424 Digital Design Automation 17 CMOS Inverter Operation August 28, 2014 204424 Digital Design Automation 18 CMOS Logic Example - Whats This? A B A B OUT +VDD GND P Transistors on when gate L N Transistors on when gate H August 28, 2014 204424 Digital Design Automation 19 VLSI Levels of Abstraction Specification (what the chip does, inputs/outputs) Architecture major resources, connections Register-Transfer logic blocks, FSMs, connections Circuit transistors, parasitics, connections Layout mask layers, polygons Logic gates, flip-flops, latches, connections August 28, 2014 204424 Digital Design Automation 20 The VLSI Design Process Move from higher to lower levels of abstraction Use CAD tools to automate parts of the process Use hierarchy to manage complexity Different design styles trade off: Design time Non-recurring engineering (NRE) cost Unit cost Performance Power Consumption August 28, 2014 204424 Digital Design Automation 21 VLSI Design Tradeoffs (1/2) Non-Recurring Engineering (NRE) Costs Design Costs Mask Tooling costs Unit Cost - related to chip size Amount of logic Current technology Performance Clock speed Implementation August 28, 2014 204424 Digital Design Automation 22 VLSI Design Tradeoffs (2/2) Power consumption - a relatively new concern Power supply voltage Clock speed
August 28, 2014 204424 Digital Design Automation 23 VLSI Design Styles Full Custom Application-Specific Integrated Circuit (ASIC) Programmable Logic (PLD, FPGA) System-on-a-Chip August 28, 2014 204424 Digital Design Automation 24 Full Custom Design Each circuit element carefully handcrafted Huge design effort High Design & NRE Costs / Low Unit Cost High Performance Typically used for high-volume applications August 28, 2014 204424 Digital Design Automation 25 Application-Specific Integrated Circuit (ASIC) Constrained design using pre-designed (and sometimes pre-manufactured) components Also called semi-custom design CAD tools greatly reduce design effort Low Design Cost / High NRE Cost / Med. Unit Cost Medium Performance August 28, 2014 204424 Digital Design Automation 26 Programmable Logic (PLDs, FPGAs) Pre-manufactured components with programmable interconnect CAD tools greatly reduce design effort Low Design Cost / Low NRE Cost / High Unit Cost Lower Performance August 28, 2014 204424 Digital Design Automation 27 System-on-a-chip (SOC) Idea: combine several large blocks Predesigned custom cores (e.g., microcontroller) - intellectual property (IP) ASIC logic for special-purpose hardware Programmable Logic (PLD, FPGA) Analog Open issues Keeping design cost low Verifying correctness of design August 28, 2014 204424 Digital Design Automation 28 Perspective on Design Styles Few engineers will design custom chips Some engineers will design ASICs & SOCs Many engineers will design FPGA systems
August 28, 2014 204424 Digital Design Automation 29 VLSI Trends: Moores Law In 1965, Gordon Moore predicted that transistors would continue to shrink, allowing: Doubled transistor density every 18-24 months Doubled performance every 18-24 months History has proven Moore right But, is the end is in sight? Physical limitations Economic limitations Im smiling because I was right! Gordon Moore Intel Co-Founder and Chairmain Emeritus Image source: Intel Corporation www.intel.com August 28, 2014 204424 Digital Design Automation 30 Microprocessor Trends (Intel) Year Chip L transistors 1971 4004 10 m 2.3K 1974 8080 6 m 6.0K 1976 8088 3 m 29K 1982 80286 1.5 m 134K 1985 80386 1.5 m 275K 1989 80486 0.8 m 1.2M 1993 Pentium 0.8 m 3.1M 1995 Pentium Pro 0.6 m 15.5M 1999 Mobile PII 0.25 m 27.4 2000 Pentium 4 0.18 m 42M 2002 Pentium 4 (N) 0.13 m 55M Source: http://www.intel.com/pressroom/kits/quickreffam.htm August 28, 2014 204424 Digital Design Automation 31 Microprocessor Trends 0 10 20 30 40 50 60 70 80 90 100 1970 1980 1990 2000 T r a n s i s t o r s
( M i l l i o n s ) Intel Motorola DEC/Compaq Alpha (R.I.P) P4 G4 Sources: http://www.intel.com/pressroom/kits/quickreffam.htm, www.geek.com August 28, 2014 204424 Digital Design Automation 32 Microprocessor Trends (Log Scale) Sources: http://www.intel.com/pressroom/kits/quickreffam.htm, www.geek.com 0.001 0.01 0.1 1 10 100 1970 1975 1980 1985 1990 1995 2000 2005 T r a n s i s t o r s
( M i l l i o n s ) Intel Motorola DEC/Compaq Alpha (R.I.P) P4N G4 P4 August 28, 2014 204424 Digital Design Automation 33 DRAM Memory Trends (Log Scale) Source: Textbook, Industry Reports 0.0625 0.25 1 4 16 64 128 256 512 0.01 0.1 1 10 100 1000 1975 1980 1985 1990 1995 2000 2005 Size (Mb) August 28, 2014 204424 Digital Design Automation 34 Processor Performance Trends Source: Hennesy & Patterson Computer Architecture: A Quantitative Approach, 3rd Ed., Morgan-Kaufmann, 2002. Vax 11/780 August 28, 2014 204424 Digital Design Automation 35 Trends in VLSI Transistor Smaller, faster, use less power Interconnect Less resistive, faster, longer (denser design) Yield Smaller die size, higher yield August 28, 2014 204424 Digital Design Automation 36 Summary - Technology Trends Processor Logic capacity increases ~ 30% per year Clock frequency increases ~ 20% per year Cost per function decreases ~20% per year Memory DRAM capacity: increases ~ 60% per year (4x every 3 years) Speed: increases ~ 10% per year Cost per bit: decreases ~25% per year August 28, 2014 204424 Digital Design Automation 37 Technology Directions: SIA Roadmap Year 1999 2002 2005 2008 2011 2014 Feature size (nm) 180 130 100 70 50 35 Logic trans/cm 2 6.2M 18M 39M 84M 180M 390M Cost/trans (mc) 1.735 .580 .255 .110 .049 .022 #pads/chip 1867 2553 3492 4776 6532 8935 Clock (MHz) 1250 2100 3500 6000 10000 16900 Chip size (mm 2 ) 340 430 520 620 750 900 Wiring levels 6-7 7 7-8 8-9 9 10 Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.5 High-perf pow (W) 90 130 160 170 175 183
August 28, 2014 204424 Digital Design Automation 38 Scaling The process of shrinking the layout in which every dimension is reduced by a factor is called Scaling. Transistors become smaller, less resistive, faster, conducting more electricity and using less power. Designs have smaller die sizes, higher yield and increased performance.
August 28, 2014 204424 Digital Design Automation 39 Can Scaling Continue? Scaling work well in the past:
In order to keep scaling work in the future, many technical problems need to be solved.
Year 1989 1992 1995 1997 1999 Technology (m) 0.65 0.5 0.35 0.25 0.18 2001 0.15 August 28, 2014 204424 Digital Design Automation 40 Can Scaling Continue? Some characteristics of the transistors do not scale uniformly, e.g., delay, leakage current, threshold voltage, etc. Mismatch in the scaling of transistors and interconnects. Interconnect delay has increased from 5-10% of the overall delay to 50-70%.
August 28, 2014 204424 Digital Design Automation 41 Roadmap International Technology Roadmap for Semi- conductors (ITRS) Projection of future technology requirements for the next 15 years.
Edition Year of Publication 1st 2nd 3rd 4th 1992 1994 1997 1999 http://public.itrs.net 5th 2001 2002 updates August 28, 2014 204424 Digital Design Automation 42 These trends have brought many changes and new challenges to circuit design. August 28, 2014 204424 Digital Design Automation 43 Complicated Design Too many transistors and no way to handle them manually. Solutions: CAD Hierarchical design Design re-use August 28, 2014 204424 Digital Design Automation 44 Power and Noise Huge power consumption and heat dissipation becomes a problem Noise and cross talk. Solutions: Better physical design August 28, 2014 204424 Digital Design Automation 45 Interconnect Area Too many interconnects Solutions: More interconnect layers (made possible by Chemical-Mechanical Polishing) CAD tools for 3-D routing
August 28, 2014 204424 Digital Design Automation 46 Interconnect Delay Interconnect delay becomes a dominating factor in circuit performance Solutions: Use copper wire Interconnect optimization in physical design, e.g., wire sizing, buffer insertion, buffer sizing. August 28, 2014 204424 Digital Design Automation 47 Interconnect Delay 0.65 1989 0.5 1992 0.35 1995 0.25 1998 0.18 2001 0.13 2004 0.1 2007 0 5 10 15 20 25 30 35 40 Gate delay Interconnect delay Source: SIA Roadmap 1997 August 28, 2014 204424 Digital Design Automation 48 Gallery - Early Processors Mos Technology 6502 Intel 4004 First P - 2300 xtors L=10 m August 28, 2014 204424 Digital Design Automation 49 Intel 4004 Introduction date: November 15, 1971 Clock speed: 108 KHz Number of transistors: 2,300 (10 microns) Bus width: 4 bits Addressable memory: 640 bytes Typical use: calculator, first microcomputer chip, arithmetic manipulation August 28, 2014 204424 Digital Design Automation 50 Gallery - Current Processors PowerPC 7400 (G4) 6.5M transistors / 450MHz / 8-10W L=0.15 m Pentium III 28M transistors / 733MHz-1Gz / 13-26W L=0.25 m shrunk to L=0.18 m August 28, 2014 204424 Digital Design Automation 51 Gallery - Current Processors Pentium 4 42M transistors / 1.3-1.8GHz / 49-55W L=0.18 m Pentium 4 Northwood 55M transistors / 2-2.5GHz L=0.13 m August 28, 2014 204424 Digital Design Automation 52 Pentium 4 0.18-micron process technology (2, 1.9, 1.8, 1.7, 1.6, 1.5, and 1.4 GHz) Introduction date: August 27, 2001 (2, 1.9 GHz); ...; November 20, 2000 (1.5, 1.4 GHz) Level Two cache: 256 KB Advanced Transfer Cache (Integrated) System Bus Speed: 400 MHz SSE2 SIMD Extensions Transistors: 42 Million Typical Use: Desktops and entry- level workstations 0.13-micron process technology (2.53, 2.2, 2 GHz) Introduction date: January 7, 2002 Level Two cache: 512 KB Advanced Transistors: 55 Million August 28, 2014 204424 Digital Design Automation 53 Intels McKinley Introduction date: Mid 2002 Caches: 32KB L1, 256 KB L2, 3MB L3 (on- chip) Clock: 1GHz Transistors: 221 Million Area: 464mm 2 Typical Use: High-end servers Future versions: 5GHz, 0.13-micron technology
August 28, 2014 204424 Digital Design Automation 54 Gallery - Current FPGA Xilinx Virtex FPGA August 28, 2014 204424 Digital Design Automation 55 Gallery - Graphics Processor nVidia GeForce4 57M transistors / 300MHz / ??W L=0.15 m August 28, 2014 204424 Digital Design Automation 56 What were going to do Chip design: MOSIS tiny chip
August 28, 2014 204424 Digital Design Automation 57 What were going to do Fabricated MOSIS Tiny Chip August 28, 2014 204424 Digital Design Automation 58 Die Photo - 2001 Design Project Chip Design by Ed Thomas Photo courtesy Ron Feiller, Agere