Finite State Machines

Ajit Pal
Professor
Department of Computer Science and Engineering
Indian Institute of Technology Kharagpur
INDIA-721302
Computer Organization and Architecture
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Agenda
Introduction
Mealy and Moore Machines
FSM Design Steps
PLA Realization
Conclusions
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Introduction
Any digital system will have some control part
Finite state machines (FSMs) are commonly used to realize control
parts
FSM provides an organized structure for capturing control sequences
and operation
An FSM can be diagrammatically represented by a state-transition
diagram
Labeled nodes represent states and labeled directed edges represent
transitions among the states
Example: Consider a sequence detector that produces 1 when five
ones appear sequentially at the input
S1
S2 S3 S4
1/0
1/0
1/0 1/0
0/0
0/0
0/0
0/0,1/1
0/0
S5
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General Model of a FSM
FSM model: (PI, PO, S, , )
PI: Set of Inputs {x1, x2, , xn}
PO: Set of Outputs {z1, z2, , zm}
S: Set of states (s1, s2, , sp)
: State Transition function S+ = (S, X)
: Output transition function Z = (S,X)
PI
PO
NS
PS
CLK
X1
Combinational logic
to compute outputs
and next states
D Flip-flops
X2
Xn
Q1
Q2
Qk
z1
z2
zm
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Mealy and Moore Machines
Mealy machine:
Outputs are dependent on
inputs and current state
Output transition function
Z = (S,X)

Moore machine:
Outputs are dependent
only on current state
Output transition function
Z = (S)
CLK
PI PO
Combinational logic
to compute outputs
and next states
Latches
NS
PS
CLK
PI
PO
Combinational logic
to compute outputs
Combinational logic to
compute next states
Latches
NS
PS
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Mealy Machine Example
The state-transition diagram of a sequence detector that
produces a 1 for each occurrence of an input sequence 0110.
The FSM has four states as shown below:
s1
s2
s3 s4
1/0
1/0
1/0
0/0
0/1
0/0
0/0 1/0
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Moore Machine Example
The state-transition diagram of a sequence detector that produces
a 1 if the sequence consists of even number of 1s and even
number of 0s
s1
EE
s2
EO
s3
OO
s4
OE
1
1
0
0
0
1
1
0
1
0
0
0
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FSM Design Steps
Step 1: The state-transition diagram:
The state machine function is captured in a state-
transition diagram
Simple checks for drawing state-transition diagram:
Ensure that all states, including the idle state, are
captured
Check that transitions for all possible input
combinations are leaving each of the states
Insert appropriate output to each transition
Insert loops into any state, with appropriate condition,
for remaining in that state
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Step 2: State minimization/reduction:
Two states of a FSM are equivalent if and only if,
for any input, they have identical outputs and the
corresponding next states are also equivalent
Only one state among the equivalent states
needs to be retained
Reduced number of states leads to simpler FSM
There exists systematic procedure to identify and
combine states having equivalent behaviour
FSM Design Steps
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Step 3: FSM State Encoding
States Codes
S1 000
S2 001
S3 010
S4 011
S5 100
In the state assignment state, each state is given a
unique code
States assignment strongly influences the complexity
of its combinational logic part
Traditionally state assignment has been used to
optimize the area and/or delay of the circuit
FSM Design Steps
S1
S2 S3 S4
1/0
1/0
1/0 1/0
0/0
0/0
0/0
0/0,1/1
0/0
S5
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FSM Design Steps
Present state

y3y2y1
Next state, output
Y3Y2Y1,z
x = 0
Next state, output
Y3Y2Y1,z
x = 1
S1 000
000,0 001,0
S2 001
000,0 010,0
S3 010
000,0 011,0
S4 011
000,0 100,0
S5 100
000,0 000,1
Step 4: State table formation
S1
S2 S3 S4
1/0
1/0
1/0 1/0
0/0
0/0
0/0
0/0,1/1
0/0
S5
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FSM Design Steps
Step 5: implementation: Two-level and multilevel logic
may be implemented using static CMOS logic gates, a
Programmable logic array (PLA) or a ROM
y3
y2
y1
Y3
Y2
Y1
PI
PO
NS
PS
CLK
Combinational logic
to compute outputs
and next states
x
z
D Q
D Q
D Q
Z = y3y2y1x
Y3 = y3y2y1x
Y2 = y3y2y1x + y3y2y1x
Y1 = y3y1x
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Realization using ROM
y3
y2
y1
Y3
Y2
Y1
PI
PO
NS
PS
CLK
ROM
x
z
D Q
D Q
D Q
Use of ROMs to
realize Boolean
functions is wasteful
in many situations
y3
DECODER
ENCODER
z
y2
y1
x
Y1Y2 Y3
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PLA Realization
X
1
X
2
X
3
Inverters
AND - plane
OR -
plane
Inverters
x
1
x
2
x
1
x
1
x
2
x
2
x
3
x
3
f
1
f
2
f
3
PLAs overcome the
wastefulness of ROM by
making the decoder
programmable

3 1 2 1 3 2 3
3 2 3 2 1 2
3 2 1 2 1 3 2 1 2 1 1
3 2 1 2 1 1




x x x x x x f
x x x x x f
x x x x x x x x x x f
x x x x x f




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Detailed PLA realization
Z = y3y2y1x,
Y3 = y3y2y1x,
Y2 = y3y2y1x + y3y2y1x,
Y1 = y3y1x.
y3 y2
y1
x
Y3 Y2 Y1
z
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Conclusion
FSMs constitute an integral part of digital systems
Two basic type of FSM models known as Mealy and
Moore machines have been introduced
Discussed how the specification of the function of
an FSM is transformed through a number of steps to
an actual implementation using gates and flip-flops
Implementation steps have been illustrated with a
running example
FSMs for counters, vending machines, traffic-light
controller, etc can be implemented in a similar
manner
Low-power FSM implementation techniques will be
discussed later
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Thanks!