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Presented by

M.KARTHIKEYAN.
To understand 16-bit Thumb mode operation of
ARM Processor.
To understand the features of Thumb mode
operation and how Thumb instructions
decompress to ARM Mode.
To know the technique of switching between ARM
and Thumb mode of operations.
To know the similarities and differences between
ARM and Thumb mode of operation
To understand exception handling and branching
in Thumb mode.
To understand operation of data processing
instructions and data transfer instructions in
Thumb mode.
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ARM7TDMI processor has two instruction sets:
the standard 32-bit ARM instruction set
a 16-bit THUMB instruction set.
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ARM state
which executes 32-bit, word-aligned
ARM instructions.

THUMB state
which operates with 16-bit, halfword-
aligned THUMB instructions.
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ARM architecture versions v4T and above
define a 16-bit instruction set called the
Thumb instruction set. The functionality of
the Thumb instruction set is a subset of the
functionality of the 32-bit ARM instruction
set.
A processor that is executing Thumb
instructions is operating in Thumb state. A
processor that is executing ARM instructions
is operating in ARM state.
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A processor in ARM state cannot execute
Thumb instructions, and a processor in
Thumb state cannot execute ARM
instructions. You must ensure that the
processor never receives instructions of the
wrong instruction set for the current state.
Each instruction set includes instructions to
change processor state.

Note: ARM processors always start executing
code in ARM state.
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The processor in Thumb mode uses same eight general-
purpose integer registers that are available ARM
mode.Some Thumb instructions also access the PC(ARM
register 15),the Link Register(ARM register 14) and Stack
Pointer(ARM register 13).
When R15 is read,bit[0] is zero and bits[31:1]contain the
PC.when R15 is written,bit[0] is IGNORED and bits[31:1] are
written to the PC.
Thumb does not provide direct access to the CPSR or any
SPSR.
Thumb execution is flagged by the T bit(bit[5]) in the CPSR.
T==0 32-bit instructions are fetched(ARM
instruction)
T==1 16-bit instructions are fetched(Thumb
instruction)

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In a typical embedded system:
use ARM code in 32-bit on-chip memory for small
speed- critical routines
use Thumb code in 16-bit off-chip memory for large
non-critical control routines
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Note:
Switching between ARM and Thumb States of Execution
Using BX Instruction
For Most Instruction Generated by the Compiler
Condition Execution is not used.
Source and Destination Registers are identical
Only low registers used
Constants are limited size
Inline barrel shifter not used

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Byte (8-bit):
placed on any byte boundary.
Half-word (16-bit):
aligned to two-byte boundaries.
Word (32-bit):
aligned to four- byte boundaries.
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Not a complete architecture
Dynamically decompressed to ARM Instruction
Fully supported by ARM development tools
Both entry and exit are done using
corresponding BX Instruction
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Default entry to exception mode is always
ARM
Explicit entry to Thumb is done using ARM
mode BX Instruction
Explicit entry back to ARM mode is done using
Thumb mode BX Instruction
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Registers r0 to r7 are accessible (Lo)
Few instructions require r8 to r15 to be
specified
r13 is used as the stack pointer
r14 is used as the link register
r15 is used as the program counter
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Thumb General registers and Program Counter
Thumb Program Status Registers
User / System FIQ Supervisor Abort IRQ Undefined
CPSR
sprsr_fiq sprsr_fiq sprsr_fiq SPSR_ABT SPSR_SVC sprsr_fiq sprsr_fiq SPSR_FIQ sprsr_fiq sprsr_fiq sprsr_fiq sprsr_fiq sprsr_fiq SPSR_IRQ
CPSR CPSR CPSR CPSR CPSR
sprsr_fiq sprsr_fiq sprsr_fiq sprsr_fiq sprsr_fiq SPSR _UND
PC
LR
SP
r7
r4
r5
r2
r1
r0
r3
r6
PC_ FIQ
r7
r4
r5
r2
r1
r0
r3
r6
LR_ FIQ
SP_FIQ
PC_ SVC
r7
r4
r5
r2
r1
r0
r3
r6
LR_ SVC
SP_SVC
PC_ ABT
r7
r4
r5
r2
r1
r0
r3
r6
LR_ ABT
SP_ABT
PC_ IRQ
r7
r4
r5
r2
r1
r0
r3
r6
LR_ IRQ
SP_IRQ
PC_ UND
r7
r4
r5
r2
r1
r0
r3
r6
LR_ UND
SP_UND
Load-store architecture
Support 8-bit byte, 16-bit half-word and 32
bit word data types with aligned boundaries
32 bit unsegmented memory.
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Unconditional Execution of instruction
2-address format for data processing
Less regular instruction formats.
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With exception processor is returned to ARM
mode.

While returning previous mode is restored as
SPSR is transferred to CPSR
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Short conditional branches

Medium range unconditional branches

Long range Subroutine calls

Branch to change to ARM Mode
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1 1 0 1 Condition 8-Bit Offset
1 1 1 0 0 11 Bit Offset
1 1 1 H 11 Bit Offset
0 1 0 0 0 1 1 1 0 H Rm 0 0 0
B <cond> <label>
B <label>
BL <label>
BX Rm
15 14 13 12 11
8 7
0
Different format for each case
Offset is reduced to 11bit and 8 bit
Offset is shifted left by 1-bit (to give half-
word alignment) and sign-extended to 32
bits.
BL is more subtle to give 22-bit offset
using link register for temporary storage
No direct mapping to ARM instructions as
Thumb require half-word aligned offsets.
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To allow for a reasonably large offset to the target
subroutine each of these two instructions is
automatically translated by the assembler into a
sequence of two 16 bit thumb instructions
1. H = 10
LR := PC + (sign-extended offset shifted left 12 places);

2. H = 11
PC := LR + (offset shifted left 1 place)

3. LR := address of next instruction
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Address of next instruction is saved in r14_svc
CPSR is saved in r14_svc
Disables IRQ, Clears T bit, Enters Supervisor
mode
PC is forced to 0x08
8 bit immediate is zero extended to fill the 24-
bit field in the ARM instruction.
Limits SWIs to first 256 of 16 million ARM
SWIs.
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1 1 0 1 1 1 1 1 8 Bit Immediate
Fairly complex instruction formats
No conditional execution
Separate shift operations provided, no shifting
of second operand
All data processing instruction set condition
code bits (no need of S)
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<op> Rd, Rn, Rm
<op> Rd, Rn, # <imm3>
<op> Rd|Rn, Rm|Rs
<op> Rd, Rn, #<sh 5>
<op> Rd, #<imm 8>
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MOV Rd, #<imm8>
MVN Rd, Rm
CMP Rn, #<imm8>
CMP Rn, Rm
CMN Rn, Rm
TST Rn, Rm
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ADD Rd, Rn, #<imm3>
ADD Rd, #< imm8>
ADD Rd, Rn, Rm
ADC Rd, Rm
SUB Rd, Rn, #<imm3>
SUB Rd, #< imm8>
SUB Rd, Rn, Rm
SBC Rd, Rm
NEG Rd, Rn
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LSL Rd, Rm, #<#sh>
LSL Rd, Rs
LSR Rd, Rm, #<#sh>
LSR Rd, Rs
ASR Rd, Rm, #<#sh>
ASR Rd, Rs
ROR Rd, Rs
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AND Rd, Rm
EOR Rd, Rm
ORR Rd, Rm
BIC Rd, Rm
MUL Rd, Rm
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ADD Rd, Rm (1 or 2 Hi registers)
CMP Rn, Rm (1 or 2 Hi registers)
MOV Rd, Rm (1 or 2 Hi registers)
ADD Rd, PC, #<imm8>
ADD Rd, SP, #<imm8>
ADD SP, SP, #<imm7>
SUB SP, SP, #<imm7>
Except others donot set condition code bits
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LDR|STR Rd, [Rn, #off5]
LDR|STR Rd, [Rn, Rm]
LDRB|STRB Rd, [Rn, #off5]
LDRB|STRB Rd, [Rn, Rm]
LDRH|STRH Rd, [Rn, #off5]
LDRH|STRH Rd, [Rn, Rm]
Signed operands:
LDR|STR {S} {H|B} Rd, [Rn, Rm]
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LDMIA|STMIA Rn!, { <reg list> }

Rn may be any register among Ro R7

Register set can be any subset of R0 R7 but
not base register Rn

Write back to base register is always
selected.
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POP|PUSH { <reg list> {, R}}

R13 (sp) is used as base register

Uses Full Descending Stack

In addition any subset of Ro-R7 registers LR
(lr) may be included in PUSH instruction and
PC (pc)may be included in POP instruction
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Translation from 16-bit Thumb instruction to
32-bit ARM instruction
Condition bits changed to always
Lookup to translate major and minor opcodes
Zero extending 3-bit register specifiers to
give 4-bit specifiers
Zero extending immediate values
Implicit S(affecting condition codes) should
be explicitly specified.
Thumb 2-address format must be mapped to
ARM 3-address format
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Thumb code requires 70% of space of ARM
code
Thumb code uses 40% more instructions than
the ARM code
With 32-bit memory ARM code is 40% faster
With 16-bit memory Thumb code is 45% faster
than ARM code
Thumb code uses 30% less external memory
power than ARM code.
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Thumb ARM mode switching
Similarities and differences
Thumb exception handling
Data processing instructions
Data transfer instructions
Separate shift instructions
Restricted stack operations.
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ARM 7TDMI
Strong ARM
ARM 9
ARM 9 TDMI
ARM 9E
ARM 10E
ARM 11
Cortex
X Scale
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