The 8051

Architecture

9/8/2014
ESI,AMG,BVCOE
2
Overview
General physical & operational features
Block diagram
Pin assignments
Logic symbol
Hardware description
Pin description
Read-modify-write port instructions
In this Lecture
The 8051 microcontroller
a Harvard architecture (separate
instruction/data memories)
single chip microcontroller (C)
developed by Intel in 1980 for use in embedded
systems.
today largely superseded by a vast range of
faster and/or functionally enhanced 8051-
compatible devices manufactured by more than
20 independent manufacturers
Harvard and von Neumann Architectures
Harvard Architecturea type of computer
architecture where the instructions (program
code) and data are stored in separate memory
spaces
Example: Intel 8051 architecture

Von Neumann Architectureanother type of
computer architecture where the
instructions(program code) and data are stored in
the same memory space
Example: Intel 8085, Intel 8086 architecture


Microprocessor (MPU)
MPU (CPU)
Read instructions
Process binary data
5
330_01
Microprocessor-Based System
6
MCU-Based Systems
Includes microprocessor, memory, I/O ports, and
support devices (such as timers) on a single
semiconductor chip

Buses are generally not available to a system
designer

I/O ports are generally multiplexed and can be
programmed to perform different functions
7
330_01
Block Diagram
330_01
8
MCU-Based system
9
330_01
Computer Architectures
Von neumann versus Harvard Architecture

CISC versus RISC processors

Microprocessors and Microcontrollers
330_01
10
Microprocessor
CPU is stand-alone, RAM,
ROM, I/O, timer are separate
designer can decide on the
amount of ROM, RAM and
I/O ports.
expansive
versatility
general-purpose

Microcontroller
CPU, RAM, ROM, I/O and
timer are all on a single chip
fix amount of on-chip ROM,
RAM, I/O ports
Highly bit addressable
for applications in which cost,
power and space are critical
single-purpose
Microprocessor vs. Microcontroller
meeting the computing needs of the task efficiently and cost
effectively
speed, the amount of ROM and RAM, the number of I/O
ports and timers, size, packaging, power consumption
easy to upgrade
cost per unit
availability of software development tools
assemblers, debuggers, C compilers, emulator, simulator,
technical support
wide availability and reliable sources of the microcontrollers.
Three criteria in Choosing a Microcontroller
Comparison of the 8051 Family Members
ROM type
8031 no ROM
80xx mask ROM
87xx EPROM
89xx Flash EEPROM
89xx
8951
8952
8953
8955
898252
891051
892051
Example (AT89C51,AT89LV51)
AT= ATMEL(Manufacture)
C = CMOS technology
LV= Low Power(3.0v)

Comparison some of the 8051 Family
Members
ROM RAM Timer
8051 4K 128 2
8031 - 128 2
8751 4K EPROM 128 2
8052 8K 256 3
8032 - 256 3
8752 8K EPROM 256 3
9/8/2014
ESI,AMG,BVCOE
15
4KB ROM
128 bytes internal RAM
4 register banks of 8 bytes each (R0-R7)
16 bytes of bit-addressable area
80 bytes of general purpose memory
Four 8-bit I/O ports (P0-P3)
Two 16-bit timers (Timer0 & Timer1)
One serial receiver-transmitter interface
Five interrupt sources (2 external & 3 internal)
One oscillator (generates clock signal)
General Physical Features of 8051
9/8/2014
ESI,AMG,BVCOE
16
Memory of 8051 can be increased externally:
Increase memory space for codes (programs) by
64K
Increase memory space for data by 64K
Boolean instructions work with 1 bit at a time
General Operational Features
The 8051 Block Diagram
Interrupt Control
External Interrupts
CPU
OSC
Timer 1
Timer 0
Serial
Port
I/O Ports
Bus
Control
Timer
Inputs
P0 P3 P1
4K byte
ROM
128 byte
RAM
P2
(Address/Data)
TXD RXD


XTAL1
XTAL2
9/8/2014
ESI,AMG,BVCOE
17
ALE
EA
PSEN
RS
T
The 8051 Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
CC

P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
8051
The 8051 Logic Symbol
VSS VCC RST
P
O
R
T
0
ADDRESS
AND
DATA BUS
XTAL1
XTAL2
ALE
EA
PSEN
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
RxD
TxD
INT0
INT1
T0
T1
WR
RD
SECONDARY
FUNCTIONS
P
O
R
T
3
P
O
R
T
2
ADDRESS
BUS
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
P
O
R
T
1
9/8/2014
ESI,AMG,BVCOE
20
1. Oscillator circuit
2. Program counter (PC)
3. Data pointer (DPTR)
4. Accumulator (A) register
5. B register
6. Flags
7. Program status word (PSW)
8. Internal memory (ROM, RAM, additional memory)
9. Stack & stack pointer (SP)
10. Special function register (SFR)
Hardware Description
The heart of the 8051
Produces clock pulses
Synchronize all 8051s internal operations
Oscillator Circuit
A single machine cycle
consists of 12 crystal pulses !
Machine Cycle
Machine cycle is the basic repetitive process that the CPU performs once
it is powered on. A machine cycle consists of a fixed number of clock
cycles (pulses). It is different for different kinds of CPU.
The 8051 family needs 12 clock cycles for a machine cycle.
The CPU takes one or more machine cycles to complete an instruction.
More complex instructions require more number of machine cycles to
complete the instruction. The number of machine cycles of the 8051
instructions are ranging from 1 to 4.
Example 4-1
Find the elapse time of the machine cycle for:
(a) XTAL = 11.0592 MHz
(b) XTAL = 16 MHz
(c) XTAL = 20 MHz
Solution:
(a) 11.0592 MHz / 12 = 921.6 kHz
T = 1 / 921.6 kHz = 1.085 s
(b) 16 MHz / 12 = 1.333 MHz
T = 1 / 1.333 MHz = 0.75 s
(c) 20 MHz / 12 = 1.667 MHz
T = 1 / 1.667 MHz = 0.60 s
9/8/2014
ESI,AMG,BVCOE
24
PC is a 16-bit register
PC is the only register that does not have an internal
address
Holds the address of the memory location to fetch the
program instruction
Program ROM may be on the chip at addresses
0000H to 0FFFH (4Kbytes), external to the chip for
addresses that exceed 0FFFH
Program ROM may be totally external for all
addresses from 0000H to FFFFH
PC is automatically incremented (+1) after every
instruction byte is fetched
Program Counter (PC)
9/8/2014
ESI,AMG,BVCOE
25
DPTR is a 16-bit register
DPTR is made up of two 8-bit registers: DPH and DPL
DPTR holds the memory addresses for internal and
external code access and external data access
(eg. MOVC A,@A+DPTR MOVX A,@DPTR MOVX
@DPTR,A )
DPTR is under the control of program instructions and
can be specified by its 16-bit name, or by each
individual byte name, DPH and DPL
DPTR does not have a single internal address; DPH
and DPL are each assigned an address (83H and
82H)
Data Pointer (DPTR)
Accumulator (A Register)
9/8/2014
ESI,AMG,BVCOE
26
Most versatile CPU register and is used for many
operations, including addition, integer
multiplication and division, and Boolean bit
manipulations
A register is also used for all data transfer
between the 8051 and any external memory
9/8/2014
ESI,AMG,BVCOE
27
B register is used with the A register for
multiplication and division operations
(eg. MUL AB DIV AB)
No other special function other than as a
location where data may be stored
B Register
Flags are 1-bit registers provided to store the
results of certain program instructions
Other instructions can test the condition of the flags
and make decisions based on the flag states
Flags are grouped inside the program status word
(PSW) and the power control (PCON) registers for
convenient addressing
Math flags: respond automatically to the outcomes
of math operations (CY, AC, OV, P)
User flags: general-purpose flags that may be used
by the programmer to record some event in the
program (F0, RS0, RS1)
Flags
PSW contains the math flags, user program flag
F0, and the register select bits (RS1, RS0) that
identify which of the four general-purpose
register banks is currently in use by the program
7 6 5 4 3 2 1 0
CY AC F0 RS1 RS0 OV -- P
Program Status Word (PSW)
Program Status Word (PSW)
Bit Symbol Function
7 CY Carry Flag; used in arithmetic, JUMP, ROTATE,
and BOOLEAN instruction
6 AC Auxiliary carry flag; used for BCD arithmetic
5 F0 User flag 0
4 RS1 Register bank select bit 1
3 RS0 Register bank select bit 0
2 OV Overflow flag; used in arithmetic instructions
1 -- Reserved for future use
0 P Parity flag; shows parity of register A: 1 = Odd
Parity
9/8/2014
ESI,AMG,BVCOE
31
A functioning computer must have memory for
program code bytes, commonly in ROM, and RAM
memory for variable data that can be altered as the
program runs
8051 has internal RAM (128 bytes) and ROM
(4Kbytes)
8051 uses the same address but in different
memories for code and data
Internal circuitry access the correct memory based on
the nature of the operation in progress
Can add memory externally if needed
Internal Memory
8051 Internal RAM Organisation
R7
R6
R5
R4
R3
R2
R1
R0
R7
R6
R5
R4
R3
R2
R1
R0
R7
R6
R5
R4
R3
R2
R1
R0
R7
R6
R5
R4
R3
R2
R1
R0
07
06
05
04
03
02
01
00
0F
0E
0D
0C
0B
0A
09
08
17
16
15
14
13
12
11
10
1F
1E
1D
1C
1B
1A
19
18
B
a
n
k

0

B
a
n
k

1

B
a
n
k

2

B
a
n
k

3

27
26
25
24
23
22
21
20
2F
2E
2D
2C
2B
2A
29
28
7F 78
77 70
6F 68
67 60
5F 58
57 50
4F 48
47 40
3F 38
37 30
2F 28
27 20
1F 18
17 10
0F 08
07 00
30
7F
Working Registers Bit Addressable General Purpose
Example
State the contents of RAM locations after the following
program:
MOV R0, #99H
MOV R1, #85H
MOV R2, #3FH
MOV R7, #63H
MOV R5, #12H
After the execution of the above program we have the
following:
RAM location 0 has value 99H RAM location 1 has
value 85H
RAM location 2 has value 3FH RAM location 7 has
value 63H
RAM location 5 has value 12H
9/8/2014
ESI,AMG,BVCOE
33
Program Status Word (PSW)
Bank Select Bits, RS1, & RS0 to select 1 of 4 register bank
9/8/2014
ESI,AMG,BVCOE
34
Example
Repeat Example using RAM addresses instead of register names.
This is called direct addressing mode and uses the
RAM address location for the destination address.
MOV 00, #99H
MOV 01, #85H
MOV 02, #3FH
MOV 07, #63H
MOV 05, #12H
9/8/2014
ESI,AMG,BVCOE
35
Example 2-7
State the contents of RAM locations after the following
program:
SETB PSW.4
MOV R0, #99H
MOV R1, #85H
MOV R2, #3FH
MOV R7, #63H
MOV R5, #12H
By default, PSW.3=0 and PSW.4=0; therefore, the instruction
SETB PSW.4 sets RS1=1 and RS0=0, thereby selecting register
bank 2. Register bank 2 uses RAM locations 10H 17H. After the
execution of the above program we have the following
RAM location 10 has value 99H RAM location 11 has value
85H
RAM location 12 has value 3FH RAM location 17 has value
63H
RAM location 15 has value 12H
7 6 5 4 3 2 1 0
CY AC F0 RS1 RS0 OV -- P
PSW
9/8/2014
ESI,AMG,BVCOE
36
9/8/2014
ESI,AMG,BVCOE
37
SP is a 8-bit register used to hold an internal RAM
address that is called the top of the stack
Stack refers to an area of internal RAM that is used in
conjunction with certain opcodes to store and retrieve
data quickly
SP holds the internal RAM address where the last
byte of data was stored by a stack operation
When data is to be placed on the stack, the SP
increments before storing data on the stack so that
the stack grows up as data is stored
As data is retrieved from the stack, the byte is read
from the stack, and then the SP decrements to point
to the next available byte of stored data
SP = 07H after reset
Stack and Stack Pointer (SP)
Stack Operation
SP = 0A
Address 0A
SP = 0A
Store Data Get Data
SP = 09
Address 09
SP = 09
Store Data Get Data
SP = 08
Address 08
SP = 08
Store Data Get Data
SP = 07
Address 07
SP = 07
Storing Data on the Stack
(Increment then store)
Internal RAM
(Get then decrement)
Getting Data From the Stack

9/8/2014
ESI,AMG,BVCOE
38
Example
Show the stack and stack pointer for the following. Assume
the default stack area.
MOV R6, #25H
MOV R1, #12H
MOV R4, #0F3H
PUSH 6
PUSH 1
PUSH 4
0B
0A
09
08
0B
0A
09
08
0B
0A
09
08
0B
0A
09
08
SP = 07



25
After PUSH 6
SP = 08


12
25
SP = 09
After PUSH 1

F3
12
25
SP = 0A
After PUSH 4
9/8/2014
ESI,AMG,BVCOE
39
Example
Examine the stack, show the contents of the registers and
SP after execution of the following instruction. All values are
in hex.
POP 3 ;POP stack into R3
POP 5 ;POP stack into R5
POP 2 ;POP stack into R2

0B
0A
09
08
0B
0A
09
08
0B
0A
09
08
54 0B
0A
09
08
54
F9
76
6C
54
F9
76
6C
F9
76
6C
SP = 0A SP = 09 SP = 08
After POP 3 After POP 5 After POP 2
Start SP = 0B
54
F9
76
6C
05
04
03
02
??
??
54
??
05
04
03
02
05
04
03
02
05
04
03
02
F9
??
54
??
F9
??
54
76
??
??
??
??
9/8/2014
ESI,AMG,BVCOE
40
Example
Show the stack and stack pointer for the following.
MOV SP, #5FH
MOV R2, #25H
MOV R1, #12H
MOV R4, #0F3H
PUSH 2
PUSH 1
PUSH 4
63
62
61
60
63
62
61
60
63
62
61
60
63
62
61
60



25


12
25

F3
12
25
Start SP = 5F SP = 60 SP = 61 SP = 62
After PUSH 2 After PUSH 1 After PUSH 4
9/8/2014
ESI,AMG,BVCOE
41
9/8/2014
ESI,AMG,BVCOE
42
8051 has 21 SFRs which occupy the addresses
from 80H to FFH (128bytes)
Not all of the addresses from 80H to FFH are
used for SFRs
Attempt to use the empty addresses may get
unpredictable result
Special Function Registers (SFR)
Special Function Registers
DATA registers

CONTROL registers

Timers

Serial ports

Interrupt system

Analog to Digital converter
Digital to Analog converter
etc..
Addresses 80h FFh

Direct Addressing is used to
access SFRs
Special Function Register Map
Bit addressable
9/8/2014
ESI,AMG,BVCOE
44
Bit Addressable RAM
Value of SFR at Reset
9/8/2014
ESI,AMG,BVCOE
46
Internal ROM
9/8/2014
ESI,AMG,BVCOE
47
Internal ROM occupies the code address space
from 0000H to 0FFFH (Size = 4K byte)
Program addresses higher than 0FFFH will
automatically fetch code bytes from external
program memory
Code bytes can also be fetched exclusively from
an external memory by connecting the external
access pin (EA) to ground
Memory mapping in 8051

ROM memory map in 8051
family
0000H
0FFFH
0000H
1FFFH
0000H
7FFFH
8051

8752

4k
DS5000-32
8k 32k
from Atmel
Corporation
from Dallas
Semiconductor
Memory Space
Address Multiplexing for External
Memory

Accessing External Code Memory
Accessing External Data
Memory
9/8/2014
ESI,AMG,BVCOE
55
VCC (pin 40 - provides supply voltage of +5V)
GND (pin 20)
XTAL1 & XTAL2 (pins 19 & 18 - to crystal and then
caps)
RST (pin 9- reset)
EA (pin 31 - external access)
PSEN (pin 29 - program store enable)
ALE (pin 30 - address latch enable)
Ports 0-3
Some Important Pins
I/O Ports (P0 - P3)
One of the most useful features of the 8051 is
that it consists of 4 I/O ports (P0 - P3)
All ports are bidirectional (they can take input and
to provide output)
All ports have multiple functions (except P1)
All ports are bit addressable
On RESET all the ports are configured as input
When a bit latch is to be used as an input, a 1
must be written to the corresponding latch by the
program to configure it as input (eg. MOV P1, #0FFH)
9/8/2014
ESI,AMG,BVCOE
56
9/8/2014
ESI,AMG,BVCOE
57
Occupies a total of 8 pins (Pins 32-39)
Can be used for :
Input only
Output only
Input and output at the same time (i.e. some pins
for input and the others for output)
Can be used to handle both address and data
Need pull-up resistors
Port 0
Port 0

9/8/2014
ESI,AMG,BVCOE
58

Port 0 as an Output Port
9/8/2014
ESI,AMG,BVCOE
59
The following code will continuously send out to
port 0 the alternating values 55H and AAH
MOV A, #55H
BACK: MOV P0, A
ACALL DELAY
CPL A
SJMP BACK
Port 0 as an Input Port
9/8/2014
ESI,AMG,BVCOE
60
In the following code, port 0 is configured first as
an input port by writing 1s to it, and then data is
received from that port and sent to P1
MOV A, #0FFH
MOV P0, A
BACK: MOV A, P0
MOV P1, A
SJMP BACK
Dual Role of Port 0
9/8/2014
ESI,AMG,BVCOE
61
When connecting an 8051 to an external memory, port 0
provides both address and data (AD0 AD7)
When ALE = 0, it provides data D0 D7
When ALE = 1, it provides Address A0 A7.
ALE is used for demultiplexing address and data with
the help of
a 74LS373 latch
9/8/2014
ESI,AMG,BVCOE
62
Occupies a total of 8 pins (Pins 1-8)
Can be used as input or output
Does not need any pull-up resistors
Upon reset, port 1 is configured as an
input port
No alternative functions
Port 1
Port 1

9/8/2014
ESI,AMG,BVCOE
63
Port 1 as an Output Port
9/8/2014
ESI,AMG,BVCOE
64
The following code will continuously send out to
port 1 the alternating values 55H and AAH
MOV A, #55H
BACK: MOV P1, A
ACALL DELAY
CPL A
SJMP BACK
Port 1 as an Input Port
9/8/2014
ESI,AMG,BVCOE
65
In the following code, port 1 is configured first as an
input port by writing 1s to it, and then data is received
from that port and saved in R7, R6, and R5
MOV P1,#0FFH
MOV A, P1
MOV R7, A
ACALL DELAY
MOV A, P1
MOV R6, A
ACALL DELAY
MOV A, P1
MOV R5, A
9/8/2014
ESI,AMG,BVCOE
66
Occupies a total of 8 pins (Pins 21-28)
Similar function as Port 1
Can be used as input or output
Does not need any pull-up resistors
Upon reset, port 2 is configured as an input port
Port 2
9/8/2014
ESI,AMG,BVCOE
67

Port 2 as an Output Port
9/8/2014
ESI,AMG,BVCOE
68
The following code will continuously send out to
port 2 the alternating values 55H and AAH
MOV A, #55H
BACK: MOV P2, A
ACALL DELAY
CPL A
SJMP BACK
Port 2 as an Input Port
9/8/2014
ESI,AMG,BVCOE
69
In the following code, port 2 is configured first as an
input port by writing 1s to it, and then data is
received from that port and sent to P1
MOV P2,#0FFH
BACK: MOV A, P2
MOV P1, A
SJMP BACK
Dual Role of Port 2
9/8/2014
ESI,AMG,BVCOE
70
When connecting an 8051 to an external memory, port 2
provides both address (A8 A15)
It is used along with P0 to provide the 16-bit address
When P2 is used for the upper 8 bits of the 16-bit address, it
cannot be used for I/O
9/8/2014
ESI,AMG,BVCOE
71
Occupies a total of 8 pins (Pins 10-17)
Similar function as Port 1 and Port 2
Can be used as input or output
Does not need any pull-up resistors
Upon reset, port 3 is configured as an input port
Pins can be individually programmable for other uses
Most commonly be used to provide some important
signals (e.g. interrupts)
Port 3
Port 3

9/8/2014
ESI,AMG,BVCOE
72
Port 3 Alternate Functions
P3 Bit Function Pin
P3.0 RxD 10
P3.1 TxD 11
P3.2 INT0 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17
I/O Port Circuitry
Read-Modify-Write Feature
A method used to access the 8051 ports
Combining all 3 actions in a single instructions :
Read the data at the port
Modify (do operation on) the data at the port
Write the results to the port
MOV P1, #55H
AGAIN: XRL P1, #0FFH
ACALL DELAY
SJMP AGAIN
9/8/2014
ESI,AMG,BVCOE
75
Read-Modify-Write Feature
Example:
ANL P1, A
ORL P2, A
XRL P3, A
JBC P1.1, LABEL
CPL P3.0
INC P2
DEC P2
DJNZ P3, LABEL
When reading a port some instructions read the
latch and others read the pin
The instructions that read the latch rather than
the pin are the ones that read a value (possibly
change it), an then rewrite it to the latch are
called read-modify-write instructions
Single-bit Addressability of Ports
One of the most powerful features of the
8051
Access only one or several bits of the port
instead of the entire 8 bits
BACK: CPL P1.2
ACALL DELAY
SJMP BACK
9/8/2014
ESI,AMG,BVCOE
77
Write the following Program
9/8/2014
ESI,AMG,BVCOE
78
1) Create a square wave of 50% duty cycle on
bit 0 of port 1.
2) Create a square wave of 66% duty cycle on
bit 3 of port1.
3) Keep monitoring pin P0.1 until it becomes
high when P0.1 becomes high,read the data
from the port 1 and send low-to-high pulse
on P0.2 to indicate data has been read.
4) A switch is connected to pin P1.0 and LED
to pin P2.7.Write a program to get the status
of the switch and send it to LED.
9/8/2014
ESI,AMG,BVCOE
79
General physical & operational features
8051 hardware description
8051 pin description
Read-modify-write port instructions
Summary
The 8051 Microcontroller and Embedded Systems
- Using Assembly and C By Mazidi
Chapter 1
Chapter 4
Microcontroller Theory and Applications By Ajay
Deshmukh
Chapter 1
Chapter 3

Read reference