1 1-

Agenda
2006 Synopsys, Inc. All Rights Reserved Synopsys 30-I-011-SSG-009
Understanding Scan Testing
1
DFTC User Interfaces
2
DFT for Clocks and Resets
4
Creating Test Protocols
3
DAY
DAY
1
2 1-
Unit O!ecti"es
After co#$leting t%is &nit' (o& s%o&ld e ale to)

*+$lain %o, to &se t%e D algorit%# to generate

a $attern t%at detects a gi"en st&ck-at fa&lt in a
co#inational design

Do t%e sa#e in a f&ll scan se-&ential design

.all of t%e fli$-flo$s are scan co#$liant' no
#e#or(' no latc%es/

*+$lain ,%( scan-c%ains are necessar( to

s&$$ort ATP0
3 1-
Unit 1 Road#a$
What is Design for
Manufactuing
Test?
D Algorithm as
applied to purely
combinational
logic
Lab 1
D Algorithm as
applied to
sequential logic
(Full can!
4 1-
"ac#aged
$ % %hips
Test
"rogram
STIL 1.0;

AT&
Fail
Pass
1%at is 2an&fact&ring Test3
"ass'Fail Testing
4 1-
Physical Defect:
A on-chip fla, introdced dring !"#ric"tion or p"c$"ging
o! "n individ"l ASI% th"t &"$es the device #alf&nction.
Co##on
P%(sical
Defects
hort
%ircuit
Transistor
Al(ays )*
)pen
%ircuit
1%at Is a P%(sical Defect3
)+ide
"inholes
5 1-
) u t p u t
h o r t e d
t o L o g i c 1
" u l l , D o ( n
T r a n s i s t o r
A l ( a y s ) *
I N
O U T
G R O U N D
P O W E R
$ n p u t
) p e n
P%(sical Defects in C2OS
T%is $%(sical "ie, of a C2OS in"erter %as se"eral defects6
7 1-
St&ck-At Fa&lt 2odel
Fault Model:
A logical #odel re$resenting t%e effects of a $%(sical defect8
SA1 Fault:
D&e to a defect' in$&t $in A
of U0 acts as if st&ck %ig%'
inde$endent of in$&t signal8
SA0 Fault:
D&e to defect' o&t$&t $in Y
of U1 acts as if st&ck lo,'
inde$endent of t%e in$&ts8
9 1-
Rules of the Game:
'ester "ccess to the device-nder-test ()*'+
is onl( "llo,ed throgh its $ri#ar( I-. ports.
R&les for Detecting a SAF
Internal Proing
of IC Too Costl(6
Internal Proing
of IC Too Costl(6
: 1-
Unit 1 Road#a$
What is Design for
Manufactuing
Test?
D Algorithm as
applied to purely
combinational
logic
Lab 1
D Algorithm as
applied to
sequential logic
(Full can!
1; 1-
Else SA0 fault is present,
and U1/Y remains at -.
Else SA0 fault is present,
and U1/Y remains at -.
T%is if < else e%a"ior can e e+$loited to detect t%e fa&lt6
Co#inational =ogic) SAF Testing
>et,ork N 1
Pri#ar(
In$&ts
Pri#ar(
O&t$&t
If this SA0 fault is not present,
then node can be driven to 1.
If this SA0 fault is not present,
then node can be driven to 1.
11 1-
D A l g o r i t h m .
1 / T a r g e t a s p e c i f c s t u c ! a t f a u l t .
0 / " r i v e f a u l t s i t e t o o p p o s i t e v a l u e .
( c o n t i n u e d )
Acti"ate t%e SA; Fa&lt .1<4/
>et,ork N 1
In$&t
Sti#&l&s
1' -
Fault,Free
Faulty 1alue
Legend
12 1-
D A l g o r i t h m .
1 / T a r g e t a s p e c i f c s t u c ! a t f a u l t .
0 / " r i v e f a u l t s i t e t o o p p o s i t e v a l u e .
2 / " r o p a g a t e e r r o r t o p r i m a r # o u t p u t .
( c o n t i n u e d )
Pro$agate Fa&lt *ffect .2<4/
The 1'- is in3erted,
but the discrepanc# is
still eas# to measure.
The 1'- is in3erted,
but the discrepanc# is
still eas# to measure.
13 1-
Anato#( of a Test Pattern .3<4/
Test Pattern:
A se/ence o! one or &ore vectors th"t "pplies "
sti#&l&s "nd chec$s !or "n e0pected res$onse to
detect " t"rget !"lt.
Test Pattern
(U1/Y SA;+
&+pected
4esponse
$nput
timulus
V e c t o r { A L L = 1 0 0 0 1 ; }
14 1-
D A l g o r i t h m .
1 / T a r g e t a s p e c i f c s t u c ! a t f a u l t .
0 / " r i v e f a u l t s i t e t o o p p o s i t e v a l u e .
2 / " r o p a g a t e e r r o r t o p r i m a r # o u t p u t .
5 / 4 e c o r d p a t t e r n $ d r o p d e t e c t e d f a u l t .
Record t%e Test Pattern .4<4/
Classic
?D
Algorit%#
Test
"rogram
for N 1
S T I L 1 . 0 ;


P t t e r ! " N 1 # $ % r & t " {
V e c t o r { }
V e c t o r { }
V e c t o r { }
V e c t o r { }
V e c t o r { A L L = 1 0 0 0 1 ; }
V e c t o r { }
V e c t o r { }
V e c t o r { }
V e c t o r { }
}
This pattern detects
the fault %&'( SA0.
This pattern detects
the fault %&'( SA0.
14 1-
Assess#ent of D Algorit%#
Ad"antages)

Deter#inistic ste$-(-ste$ #et%od of detecting SAFs

*+%a&sti"e@s&cceeds &nless a fa&lt is &ndetectale

=i#itations)

0enerates a test for one st&ck-at fa&lt at a ti#e

In"ol"es decision #aking at al#ost e"er( ste$

2a( acktrack e+cessi"el( for %ard-to-test fa&lts

15 1-
What To Do.
%se the D algorithm to generate a test pattern b# hand to detect the A1 fault.
)ecord #our test pattern *both
stimulus and response+ at right.
*+ercise) Detect SA1 Fa&lt
V e c t o r { A L L = _ _ _ _ _ _ _ ; }
17 1-
1
1
1
1
-
Sol&tion) Detect SA1 Fa&lt
Legend.
Input N is a don,t!care *0 or 1+.
-utput ' is don,t!strobe *mas+.
N - (con6ict!
-
-'1
V e c t o r { A L L = ; }
111N0 '0
19 1-
N
f
= 2 ( N
p i n s
+ N
p o r t s
)
= 2 ( 1 1 + 5 )
= 3 2
Total
Fa&lt
Co&nt
>et,ork N 1
Ao, 2an( St&ck-At Fa&lts3
1: 1-
Eui!alent Faults:
A set o! !"lts ,hose e!!ects c"nnot #e distingished
"t the A'1 "re e-&i"alent to one "nother. >o test
p"ttern e0ists th"t c"n tell the& "p"rt.
*-&i"alent Fa&lts .1<4/
>et,ork N 1
Fanout!free net.
Fanout!free net.
U1/A SA& U1/Y
SA0.
U1/A SA& U1/Y
SA0.
ATP. /ors left to right,
thinning e0uivalent faults.
ATP. /ors left to right,
thinning e0uivalent faults.
2; 1-
N
f
= 2 ( N
i n p u t s
+ 1 )
= 6
N
f
= ( N
i n p u t s
+ 2 )
= 4
After
Colla$sing
Before
Colla$sing
*-&i"alent Fa&lts .2<4/

T%e effect of a >A>D in$&t SA; is identical to t%e

o&t$&t SA1

T%e fa&lt set C A SA;' $ SA;' Y SA1 D is t%&s an

e-&i"alent set

Onl( one of t%e e-&i"alent fa&lts needs to e incl&ded

*+a#$le) Y SA1
21 1-
*-&i"alent Fa&lts .3<4/
>et,ork N 1
Fault "olla#sin$:
2y testing !or only one !"lt per e/iv"lence set, yo redce
(or colla$se+ the !"lt popl"tion. 'his &e"ns !e,er p"tterns.
After collapsing,
onl#
7 of 20 faults left.
After collapsing,
onl#
7 of 20 faults left.
22 1-
*-&i"alent Fa&lts .4<4/
Fa&lts e-&i"alent to t%e last entr( are indicated ( ((#arks8
&1 DS A
&1 (( %#!!)/A
&1 DS %#*!+/,
&0 (( %#*!+/A
&0 (( $
&1 (( %#!!)/$
&0 DS %#!!)/,
&0 (( %#!or-/A
&0 DS ,
&0 (( %#!or-/,
&1 (( %#!or-/A
&1 (( %#!or-/$
&1 (( %#!!)/,
&0 (( %#!!)/A
... .. ...
&1 DS A
&1 (( %#!!)/A
&1 DS %#*!+/,
&0 (( %#*!+/A
&0 (( $
&1 (( %#!!)/$
&0 DS %#!!)/,
&0 (( %#!or-/A
&0 DS ,
&0 (( %#!or-/,
&1 (( %#!or-/A
&1 (( %#!or-/$
&1 (( %#!!)/,
&0 (( %#!!)/A
... .. ...
E0uivalent
Fault Set
E0uivalent
Fault Set
23 1-
U 1
U .
U /
U 0
$
Y
0
A
1 ' -
Undetectale Fa&lts
To a"oid an o&t$&t glitc%' designer %as added gate U1.
It does not alter t%e f&nction Y' and is t%&s red&ndant8
Since U1 %as no effect' t%e SA; fa&lt is &ndetectale8
>et,ork N 2
8ndetectable
Stuc!At Fault
8ndetectable
Stuc!At Fault
)edundant
.ate U1
)edundant
.ate U1
Fan!-ut
Present
Fan!-ut
Present
24 1-
Test and Fa&lt Co"erage For#&las
Test Co"erage E
DT F .PT G $tHcredit/
all fa&lts - .UD F .AU G a&Hcredit//
Fa&lt Co"erage E
DT F .PT G $tHcredit/
all fa&lts
$tHcredit E 4;I ( defa&lt
a&Hcredit E ;I ( defa&lt
24 1-
U!co112&e) St%c3 4%1t S%55r6 Re2ort
(((((((((((((((((((((((((((((((((((((((((((((((
7%1t c1&& co)e 87%1t&
(((((((((((((((((((((((((((((( (((( (((((((((
Detecte) DT 1.9:;9
Po&&*<16 )etecte) PT =/
U!)etect<1e UD =:;:
ATPG %!te&t<1e AU .>10
Not )etecte) ND .:;
(((((((((((((((((((((((((((((((((((((((((((((((
tot1 7%1t& 1=:.90
te&t co+er?e @;.0.A
(((((((((((((((((((((((((((((((((((((((((((((((
I!7or5t*o!B TCe te&t co+er?e <o+e 56 <e *!7er*or
tC! tCe re1 te&t co+er?e D*tC c%&to5*-e)
2rotoco1 !) te&t &*5%1t*o! 1*<rr6.
Test Co"erage *sti#ate Re$ort
Test 1overage
Test 1overage
25 1-
Test Esca#es:
3"rts th"t $ass every test,
#t still h"ve &ndetected
de!ects th"t re"ch sers4
Is Aig% Co"erage >eeded3
Defect %e!el:
'he fraction o! test esc"pes, in
de!ective p"rts per &illion (DP2+.
27 1-
Aig% Co"erage Is =o, DP2
Jo& need %ig% fa&lt co"erage to kee$ defect le"els lo,6
Process
Jield
;
1;;;;
2;;;;
3;;;;
4;;;;
4;;;;
5;;;;
7;;;;
9;;;;
1;;I :9I :5I :4I :2I :;I
Fault %o3erage
Defecti"e
Parts $er
2illion
4;I
5;I
7;I
9;I
:;I
Escapes
0.&2
Escapes
0.&2
Defect =e"el
"ers&s
Fa&lt Co"erage
29 1-
D8T
)ne or *one
Faults Present
)ne or *one
Faults Present
T%e Single
St&ck-At Fa&lt
Ass&#$tion
Single SAF Ass&#$tion .SSAF/

T%ere is a $ossiilit( t%at #&lti$le fa&lts in t%e ASIC

can #ask o&t fa&lts tested &sing t%e SSAF ass&#$tion

T%e likeli%ood of si#&ltaneo&s SAFs is ignored

Testing for #&lti$le SAFs is too ti#e cons&#ing

T%e SSAF ass&#$tion is one $ossile reason for test

esca$es
2: 1-
Unit 1 Road#a$
What is Design for
Manufactuing
Test?
D Algorithm as
applied to purely
combinational
logic
Lab 1
D Algorithm as
applied to
sequential logic
(Full can!
3; 1-
Testing Se-&ential Designs
Jo& still need to acti"ate t%e fa&lt and $ro$agate its effect8
Re$lace eac% flo$ ,it% a testale fli$-flo$8
T%is re$lace#ent allo,s serial loading < &nloading of its8
Can t%e D algorit%# %andle fli$-flo$s3
*#edded
>et,ork N 1
Target
Fa&lt
Pre-Scan
Design
31 1-
Scannale
*-&i"alent
!or .rdin"ry
) 5lip-5lop
2&lti$le+ed
Fli$-Flo$
Sc"n Style
Scannale *-&i"alent Fli$-Flo$

T%e scan e-&i"alent %as a serial $at% fro# $in SI to SO

T%is $at% is enaled onl( d&ring testing' ( asserting SE

SE
0
1
E/SO
D E
0LF
SI
D
0LF
32 1-
9ou stitch together a serial path through all the scan 6ops:
enabling AT& to preload registers and capture responses;
9ou stitch together a serial path through all the scan 6ops:
enabling AT& to preload registers and capture responses;
T%e F&ll Scan Strateg(
Seriall( &nload fa&lt effect at PO
T%en ca$t&re t%e
fa&lt effect .1/0/
into t%is register8
Seriall( $reload register
,it% t%e sti#&l&s' &000.
33 1-
Scan Testing Protocol) *+a#$le 1
Scan S%ift Scan S%ift
Ca$t&re
S*
C=K
SI
SO
1 ; ; ;
>e+t Test Pattern

Res&lts Fro# Pre"io&s Test Pattern
1
'est here !or
" SA. !"lt
1' -
-
-
-
1
1' -
S*
C=K
SI
SO
PI1
PI2
PI3
PI4
PO1
PO2

34 1-
Scan Testing Protocol) *+a#$le 2
Scan S%ift Scan S%ift
Ca$t&re
S*
C=K
PO1
SI ; >e+t Test Pattern

PI1

;
1
1' -
1' -
S*
C=K
SI
SO
PI1
PI2
PI3
PI4
PO1
PO2
-

1
-' 1

Test a node in
t%is logic clo&d
for a SA1 fa&lt
34 1-
/ / /
% a p t u r e
c a n h i f t
% a p t u r e
/ / /
Pattern n
Pattern (n 1)
O"erla$$ing C(cles
Test Patterns O"erla$
Scanning o&t of $re"io&s $attern o"erla$s scanning in of ne+t
@for all &t first and last $atterns in t%e test $rogra#8
35 1-
Scan Strategies S&##ariLed
'est Str"tegy
'est Str"tegy
>o ScanGG
5ll Se/enti"l A'3G
>o ScanGG
5ll Se/enti"l A'3G
F&ll Scan
%o&#in"tion"l A'3G
F&ll Scan
%o&#in"tion"l A'3G
Al#ost-F&ll Scan
5"st-Se/enti"l A'3G
Al#ost-F&ll Scan
5"st-Se/enti"l A'3G

Aig%est Co"erage

2ost Scan I#$act

=ess Scan I#$act

Aig% Co"erage

=onger R&n Ti#e

=ongest R&n Ti#e

2oderate Co"erage

S$ecial A$$lications
(e.g. r"d-h"rd logic+
37 1-
Unit 1 Road#a$
What is Design for
Manufactuing
Test?
D Algorithm as
applied to purely
combinational
logic
Lab 1
D Algorithm as
applied to
sequential logic
(Full can!
39 1-
Unit S&##ar(
F&ll Scan Ad"antages)

>eeds onl( co#inational ATP0 .D Algorit%#/

for testing all SAFs

Co#inational ATP0 gi"es s%orter ATP0 r&n ti#es

Predictale and a$$lies across #ost arc%itect&res

0i"es %ig%est fa&lt co"erage of all t%e algorit%#s

*asiest to i#$le#ent
F&ll Scan =i#itations)

Adds nonf&nctional $ins to t%e $ackage

Ti#ing and densit( i#$act of scan-e-&i"alent flo$s

>ot a$$licale to e#edded #e#or(' latc%es'

fli$-flo$s not incl&ded on t%e scan-c%ain
3: 1-
=a 1) Co#$lete Flo,
DFT C%eck
Test-Read( Co#$ile
Ti#ing' Area
Read RT= Design
Miolations3 Create Test Protocol
Constraints
2et3
DFT C%eck
S$ecif( Scan Pat%s
Pre"ie,
Co"erage
Insert Scan Pat%s
Read Design and
Test Protocol Miolations3
Miolations3
Aandoff Design
Un#a$$ed
DFT Flo,
2a$$ed
DFT Flo,
Start
*nd
4; 1-
=a 1) Fro# Reading to Aandoff
After co#$leting t%is la' (o& s%o&ld e ale to)

Identif( t%e $ri#ar( ste$s in r&nning t%e tool

Identif( t%e $ri#ar( co##and for e"al&ating

tool transfor#ations

Find o&t t%e $&r$ose and s(nta+ of

co##ands and "ariales
3; #in&tes