EC303- COMPUTER ARCHITECTURE AND

ORGANIZATION
CHAPTER 4
ARITHMETIC LOGIC UNIT (ALU)
INTRODUCTION
The ALU is the part of the computer that actually
performs arithmetic and logical operations on
data. All of the other elements of the computer
system-control unit, registers, memory, I/O are
there mainly to bring data into the ALU for it to
process and then to take the results back out.
An ALU and, indeed, all electronic components in
the computer are based on the use of simple
digital logic devices that can store binary digits
and perform simple Boolean logic operations.
4.1.1 Integer Representation
Only have 0 & 1 to represent everything
8 bits word could be used to represent the non-negative numbers from 0
to 255.
Positive numbers stored in binary
e.g. 41=00101001
No minus sign and No period (radix point) for computer storage and
processing
General - n-bit sequence: a
n-1
a
n-2
..a
1
a
0
is interpreted as unsigned integer
A, then

n-1

A = 2
i
a
i


i=0

Representation of negative integers - Sign-Magnitude, ones complement,
Twos complement, Biased

Left most bit is sign bit
0 means positive
1 means negative
+24 = 00011000
-24 = 10011000
n-2

A = 2
i
a
i ,
if a
n-1
=0

i=0

General case A =
n-2

A = - 2
i
a
i ,
if a
n-1
= 1

i=0
The rule for forming the negation of an integer is invert
the sign bit.

Conversion Between different bit
lengths
For taking n-bit integer and store in m bits,
m>n
For sign- magnitude, move the sign bit to the
new left-most position and fill in with zeros.
+18 = 0001 0010 (sign magnitude,8bits)
+18=0000 0000 0001 0010 (16 bits)
-18= 1001 0010 (8 bits)
-18=1000 0000 0001 0010 (16 bits)

4.12 Design Binary Half Adder and Full Adder Using Boolean
Algebra
HA X
Y
S
C
HA X
Y
S
C
x
y
c
c
s
4.13 Manipulate Full Adder Gate Level To Create a
Parallel Binary Adder
Adding bigger binary numbers
A half adder has 4 logic gates
A full adder has two half adders plus a OR gate
Total of 9 logic gates
To add n bit binary numbers, you need 1 HA and n-1 FAs
To add 32 bit binary numbers, you need 1 HA and 31 FAs
Total of 4+9*31 = 283 logic gates
To add 64 bit binary numbers, you need 1 HA and 63 FAs
Total of 4+9*63 = 571 logic gates
15
4.14 Modify the Parallel Binary Adder to do Addition and
Subtration in a parallel Arithmetic Element
4.15 Operation of a Binary Coded Decimal Adder Using Full
Binary Adder and Half Binary Adder Block
4.2 Shift Register in ALU
Introduction
Shift registers are a type of sequential logic circuit,
mainly for storage of digital data. They are a group
of flip-flops connected in a chain so that the
output from one flip-flop becomes the input of
the next flip-flop.
Most of the registers possess no characteristic
internal sequence of states. All flip-flop is driven
by a common clock, and all are set or reset
simultaneously.
Shift Register Operation
Shift registers, like counters, are a form of sequential logic. Sequential logic, unlike
combinational logic is not only affected by the present inputs, but also, by the prior history.
In other words, sequential logic remembers past events.
Shift registers produce a discrete delay of a digital signal or waveform. A waveform
synchronized to a clock, a repeating square wave, is delayed by "n" discrete clock times,
where "n" is the number of shift register stages. Thus, a four stage shift register delays
"data in" by four clocks to "data out". The stages in a shift register are delay stages,
typically type "D" Flip-Flops or type "JK" Flip-flops.
Serial data transmission, over a distance of meters to kilometers, uses shift registers to
convert parallel data to serial form. Serial data communications replaces many slow
parallel data wires with a single serial high speed circuit.
Serial data over shorter distances of tens of centimeters, uses shift registers to get data
into and out of microprocessors. Numerous peripherals, including analog to digital
converters, digital to analog converters, display drivers, and memory, use shift registers to
reduce the amount of wiring in circuit boards.
Some specialized counter circuits actually use shift registers to generate repeating
waveforms. Longer shift registers, with the help of feedback generate patterns so long that
they look like random noise, pseudo-noise.
Basic shift registers are classified by structure according to the following types:
Serial-in/serial-out
Parallel-in/serial-out
Serial-in/parallel-out
Universal parallel-in/parallel-out
Ring counter

Serial in/serial out shift register
Serial-in, serial-out shift registers delay
data by one clock time for each stage.
They will store a bit of data for each
register. A serial-in, serial-out shift register
may be one to 64 bits in length, longer if
registers or packages are cascaded.
Serial in/serial Out shift register using type D flip-
flop
Serial in/parallel out shift register
A serial-in/parallel-out shift register is
similar to the serial-in/ serial-out shift
register in that it shifts data into internal
storage elements and shifts data out at the
serial-out, data-out, pin. It is different in that
it makes all the internal stages available as
outputs. Therefore, a serial-in/parallel-out
shift register converts data from serial
format to parallel format. If four data bits
are shifted in by four clock pulses via a
single wire at data-in, below, the data
becomes available simultaneously on the
four Outputs Q
A
to Q
D
after the fourth clock
pulse.



Parallel in/parallel out shift register
The purpose of the parallel-in/ parallel-out
shift register is to take in parallel data, shift it,
then output it as shown below. A universal
shift register is a do-everything device in
addition to the parallel-in/ parallel-out
function.



4-bit Parallel-Access Shift Register
(74HC195)

The 74HC195 can be used for parallel in/parallel out
operation, serial in/serial out and serial in/parallel
out operations. Q3 is the output when it is used for
parallel in/serial out operation.

4.2.1 Draw the shift register
(SN74195) gate level and Operation
Timing Diagram
4.2.2 Explain the shift Register Operation
FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the functional characteristics
of the LS195A 4-Bit Shift Register. The device is useful in a wide variety of
shifting, counting and storage applications. It performs serial, parallel,
serial to parallel, or parallel to serial data transfers at very high speeds.

The LS195A has two primary modes of operation, shift right (Q0 " Q1) and
parallel load which are controlled by the state of the Parallel Enable (PE)
input. When the PE input is HIGH, serial data enters the first flip-flop Q0
via the J and K inputs and is shifted one bit in the direction Q0 " Q1 " Q2
"Q3 following each LOW to HIGH clock transition. The JK inputs provide
the flexibility of the JK type input for special applications, and the simple D
type input for general applications by tying the two pins together.
When the PE input is LOW, the LS195A appears
as four common clocked D flip-flops. The data on the parallel
inputs P0, P1, P2, P3 is transferred to the respective Q0, Q1,
Q2, Q3 outputs following the LOW to HIGH clock transition.
Shift left operations (Q3 "Q2) can be achieved by tying the Qn
Outputs to the Pn1 inputs and holding the PE input LOW.

All serial and parallel data transfers are synchronous,
occurring after each LOW to HIGH clock transition. Since the
LS195A utilizes edge-triggering, there is no restriction on the
activity of the J, K, Pn and PE inputs for logic operation
except for the set-up and release time requirements.
A LOW on the asynchronous Master Reset (MR) input sets
all Q outputs LOW, independent of any other input condition.
4.3 Logical Operations in Arithmetic Logic Unit (ALU)
four possible
operations:
4 bit arithmetic logic unit
4.4 Multiplexers in Arithmetic Logic Unit
Multiplexer(Mux)
A combinational circuit that receives binary information from one of 2
n

input data lines and directs it to a single output line
A 2
n
-to 1 multiplexer has 2
n
input data lines and
n input selection lines
8-input Digital Multiplexer - ability to select one bit of data from up to eight
sources.

Attaching the 8 source pins to digital sources / streams of information allows
the designer to very easily select which source to enable, by use of three
selecting pins, the result will appear on the chip's output.


The ability to select one bit of data from up to eight sources.
Multiplexer(Mux)
A combinational circuit that
receives binary information from
one of 2
n
input data lines and
directs it to a single output line

A 2
n
-to 1 multiplexer has 2
n
input
data lines and n input selection
lines
4.4 Multiplexers in Arithmetic Logic Unit
4.4.2 Design Eight Input Multiplexers Gate Level
4.4.3 Design Two Multiplexers in a Single IC (SN54153)
Two multiplexers in single IC
(SN541543)
Two multiplexers in single IC at gate level
4.4.4 Sketch the Connection Between Four Flip-flop
Register and Multiplexer Blocks