Sie sind auf Seite 1von 66

I/O Buffer Modeling Class

2 lectures
Prerequisite Reading Chapter 7
IBIS spec will be used as
reference
Additional Acknowledgement to Arpad Muranyi, Intel Corporation
1

Additional Information
URLs
IBIS home page:
http://www.eigroup.org/ibis/ibis.htm
IBIS 3.2 spec:
http://www.vhdl.org/pub/ibis/ver3.2/
IBIS-X: http://www.eda.org/pub/ibis/futures/

Tools
Golden Parser:
http://www.eda.org/pub/ibis/ibischk3
Visual IBIS editor, SPICE-to-IBIS tool on IBIS
web site. We will use this free tool.
http://www.mentor.com/hyperlynx/visibis.cfm

Key Topics

What is a model?
Importance of accurate models
Types of buffer models
IBIS and the portions of an IBIS model
How model data is generated
How to calculate VOL and VOH from a model
Package modeling in IBIS
IBIS HSPICE example
Bergeron diagrams

Theories, Modeling, and Reality


I take the positivist viewpoint that a physical theory is
just a mathematical model and that it is meaningless to
ask whether it corresponds to reality. All that one can
ask is that its predictions should be in agreement with
observation. 1
1 Steven W. Hawking, September 30 1994, Public Lecture
on Time and Space
Electrical models can be derived in two ways
From physical structures and properties
From observed behavior

It is irrelevant whether the electrical models


correspond to physical reality.
It only needs to predict behavior.
Hence all models are behavioral

What is a Model?

Electrical representation of a physical device


For example, a transmission line can be modeled as:
A package can be modeled as a combination of transmission

lines and lumped elements.


An input or output buffer can be modeled in various ways as
well.

Importance of Accurate Models


T-lines, package, connectors, vias, return paths, etc.

can all be modeled to extreme detail, but if the


input (stimulus) is not accurate, its wasted.
Garbage in, garbage out.

It is extremely important for engineers to

understand the origins of model data, be familiar


with modeling types and limitations, and doublecheck models, whether they create them or they
receive them from someone else!
Also, know how your tool uses model data!

How do we model I/O buffers?


Description

Intellectual
Property

Simulation
Speed

Sweep-ability

Very Little

Fast

Very

Little

Fast

Somewhat

Lots

Slowest

limited

RHigh
Linear
Models

RS

More detail

RLow

Behavioral
Models

Linear or non-linear
I-V and V-t data

Transistor
Circuit /
Netlist

All buffer details including


driving transistors, pre-driver
circuitry, receiver diff. amp,
etc.

Basic C-MOS Buffer Model


Output / Driver
Pull-up
Device

Pull-down
Device

Input / Receiver
ESD Diodes
+
Inherent Diodes in Transistors

Pad Capacitance

Review Lattice Diagram Analysis


r

source

V(source)
0

Time

Vlaunch

Vlaunch

A signal can be
V(load) determined by just
knowing Vlaunch,
rload, and rsource plus
0
delay

load

N ps
Vlaunch rload
Vlaunch(1+rload)

2N ps

Time

Vlaunch rloadrsource
Vlaunch(1+rload +rload rsource)

3N ps
Vlaunch r2loadrsource

Vlaunch(1+rload+r2loadrsource+ r2loadr2source)

4N ps
Vlaunch r2loadr2source

V(load)
V(source) Zo
Vs
Rs
TD = N ps
Vs
Rt

5N ps

10

Refining Buffer Assumptions

The original assumption was that Vlaunch, rload


and rsource are constant in time and linear.
Most buffers are not linear.

In other words, there is a current dependent


voltage that changes with the time varying
voltage.
We call these I-V curve elements instead of
resistors, capacitors, or inductors
Vintial

Vs

ZL
ZL Z0

rload

ZL Z0
ZL Z0

and

ZL

and

Zload ( V I)

ZS

then

Vintial

Zload ( V I)
Vs
r
Zload ( V I) Z0 load

ZS Z0
ZS Z0

rsource

Zsource ( V I)
then

Zload ( V I) Z0
Zload ( V I) Z0

rsource

Zsource ( V I) Z0
Zsource ( V I) Z0

Beginning of Behavioral Buffer Modeling

11

Consider that Vs is Vs(t) and V is V(t), so Vintial, rload, and


rsource are Vinitial(t), rload(t), and rsource(t). Also, the
propagation functions can be described in a similar manner.
Hence the voltage and current response and for all nodes
in the network can be determined by replacing the buffer
with the appropriate I-V impedance functions and dont
require the actual transistor models for the buffer.

This was the basis for


a buffer specification
that was created in
the early 90s called
IBIS

IBIS and Other Model Types


IBIS = I/O Buffer Information Specification
The beginnings of IBIS occurred at Intel during

Pentium Pro days. Engineers wanted a way to give


buffer information to customers, and decided on I-V
curves. The initial IBIS spec was created shortly
thereafter. IBIS went through many iterations,
eventually adding V-t curves (rev 2.1) and other
features like staged devices (rev 3.0). The current
revision is 3.2.
Other I-V/V-t model types include:
Various simulator vendors have their own internal models.
However most will convert IBIS to their internal format.

We often use controlled switched resistors (V-t curves of


sorts) in SPICE.

Colloquial Terminology ~ V-t = V/T = V(t);


I-V = I/V = I(V)

12

13

What is in an IBIS file?

First IBIS is a standard for


describing the analog
behavior of the buffers of
digital devices using plain
ASCII text formatted data

IBIS files are really not


models, they just contain the
data that will be used. Casually
they may be referred to as a
models but are really
specifications.
Simulation tools interpret this
behavioral specification to
implement their own models and
algorithms

Key
areas
of
spec

Key Portions of an IBIS Model

14

ESD Diodes
+
Inherent Diodes in Transistors

Output / Driver

Vcc

Pull-up
Device
I(V)
V(t)

I(V)

I(V)
V(t)

I(V)

Pull-down
Device

Vss may
be 0V

Input / Receiver

P
a
c
k
a
g
e

P
a
c
k
a
g
e
Die Pad Capacitance

Vcc
I(V)

I(V)

Vss may
be 0V

MOS I-V Curves

15

Impedance of a buffer is dynamic during transitions - between fully open

and fully driving (RON).


Example lets take a look at a high-to-low transition below.
In the next few slides we will learn how we can model this dynamic
V-I characteristic.
VGS
VCC

VOUT (t=0) = VCC


VGS (t=0) = 0

Source

VT

Gate
Drain
Drain
Gate

Vcc

+
VGS
-

ID
Source

ID
Triode
(Ohmic)

time

0 1 2 3 4 5

VDS =
VOUT

Saturation

t=3
t=4

t=5

Vss

t=2
VCC

t=0, t=1
(no current
below Vt)

Assume pulled up to Vcc at t=0

Generating pull down I-V Data


Pull-down I-V
Measurement or Simulation Setup

16

+I

Driving
LOW

(N-channel
curve)
Pull-up
Device
on

Pull-down
Device
off

Sweep V
Vcc to 2Vcc

Output / Driver

I(V)
V(t)

I(V)

I(V)
V(t)

I(V)

Current is
positive above
Vss per
definition if I
flows

17

Generating Ground Clamp I-V Data


Ground Diode I-V
Measurement or Simulation Setup
I
+I
V

Tristate
Sweep V
Vcc to 2Vcc

Output / Driver
Pull-up
Device
on

Pull-down
Device
off

I(V)
V(t)

I(V)

I(V)
V(t)

I(V)

Current is
negative below
Vss per
definition if I
flows

Generating pull up I-V Data


Pull-up I-V
Measurement or Simulation Setup
Driving
HIGH

18

+I

V
Vcc

Sweep V
Vcc to 2Vcc

(P-channel
curve)

Output / Driver
Pull-up
Device
on

I(V)
V(t)

I(V)
V(t)
Pull-down
Device
off

I(V)

I(V)

Current is
negative below
Vcc per definition
if I flows.
It is desirable to
make the curve
referenced to
Vcc. Will explain
later

19

Generating Power Clamp I-V Data


Pull up diode I-V
Measurement or Simulation Setup

Power
Clamp
V

+I
Tristate
Sweep V
Vcc to 2Vcc

Output / Driver
Pull-up
Device
on

Pull-down
Device
off

I(V)
V(t)

I(V)

I(V)
V(t)

I(V)

Current is
positive above
Vcc per
definition if I
flows
It is desirable to
make the curve
referenced to Vcc.
Will explain next

Double Counting Resolution

20

Sometimes the clamp current is not zero in

the range of operation.


Before use in IBIS the clamp current needs
to be subtracted.
Below is an example for the ground clamp and
pull down data
I(V)
V(t)

I(V)
V(t)

I(V)
V(t)

I(V)

I(V)
V(t)

I(V)

Pull up
measurement

I(V)

I(V)
V(t)

I(V)

I(V)

I(V)

Power
Clamp

V
Vcc

I(V)
V(t)

Vcc

I
Vcc
Pull up
curve

I-V Curves in IBIS

21

IBIS uses Vcc-referenced I-V curves for all devices

hooked to the power rail (pull-up and high-side diode).


This effectively shifts and flips the I-V curve.
Major reason is so same model can be used regardless
of power connection (independent of Vcc).
For example, a 5-V and 3.3-V part can use the same model.
Measured Curve
I

IBIS Curve
I

Vcc
Vcc

Driving
HIGH

Vcc

Pull-up
Pull-up
Sweep V
Vcc to 2Vcc
+I

Power
Clamp

Power
Clamp
V

I
V

Simple model of High/Low drive


I-V

I(V)
V(t)

I(V)
V(t)

I-V

Controls V(t)
for High Curve
Controls V(t)
for Low Curve

The high and low switches are ideally


complementary

They switch in opposite senses simultaneously

Real devices have slightly different switching


characteristics.

22

How to Generate the V-t Data


Pull-up V-t
Measurement or Simulation Setup

23

VCC
VOH

VCC
VOH

Driver

RLOAD
(typically 50 ohms)
t

Pull-down V-t
Measurement or Simulation Setup

VCC

VCC

Vcc

RLOAD
(typically 50 ohms)
VOL

Driver

VOL
t

4 V-t curves are required

2 for each switch for high and low switching

Accuracy is improved if Rload is within 20% of the usage model


load

Why Four V-t Curves?

24

It is important for the V-t curves to be time-correlated.


The four V-t curves describe the relative switching
times of the pull-up and pull-down devices.
NMOS is
completely OFF

PMOS is
completely ON

PMOS begins
turning OFF

NMOS begins
turning ON

VCC

VOH

All V-t curve measurements


or simulations are started
at time zero.

VOL

NMOS begins
turning OFF

PMOS begins
turning ON

PMOS is
completely OFF

NMOS is
completely ON

More on IBIS transition time

Two ways to synchronize switch


Build delay into curves
Use version 3.1 Scheduled drivers

Make sure the total transition time to

settling is shorter that half the period.

Start of bit time

25

PVT Corners
PVT = Process, Voltage, Temperature
Models in the past have historically been built at the
corners. All buffer characteristics are considered
dependent parameters with respect to PVT.
Fast Corner = Fast process, high voltage, low temp.
Slow Corner = Slow process, low voltage, high temp.

These can be entered into an IBIS model in the min and


max columns.

Fast/strong in the max column


Slow/weak in the min column

In recent generations we have found that just providing fast


and slow corners does not adequately cover all effects. In
these cases other model types can be given (e.g., max
ringback model).
Compensated buffers explode the combination of required
buffer corners.

They use extra circuits to counteract (compensate) PVT effects


This makes PVT and buffer characteristics independent
parameters.

26

Envelope or Spec Models

27

Historically, we have repeatedly predicted buffer


strength and edge rates incorrectly.

Buffer strengths are often weaker in silicon.


Edge rates are often slower in silicon.

One approach that can be used is to create


envelope or spec models. For example:
I

Envelope.
All measured curves should
fall within these specs.

Strong

Weak

Key point!!!:
These spec curves can be
given to I/O designers to
describe required buffer
behavior.

28

Issues with spec curve models


I

Envelope.
All measured curves should
fall within these specs.

Strong

Instantaneously
a short

Weak

Instantaneously
an open

Non-monotonic

These are legal according to the spec.


Sometimes more qualification is
required.

Example: Create CMOS Model


Given:

Vcc = 2.0 V
Measurement threshold = 1 V; VIL = 0.8 V; VIH = 1.2 V
NMOS RON = 10 ohms
PMOS RON = 10 ohms
All edge rates are ramps of 2 V/ns
Capacitance at the die pad of the buffer = 2.5 pF
Clamps are 1 ohms and start 0.6V above and below rails
PMOS starts turning on 100 ps after NMOS starts turning
off (rising edge)
NMOS starts turning on 100 ps after PMOS starts turning
off (falling edge)

Will use Mentor Graphic Visual IBIS editor in


example

http://www.mentor.com/hyperlynx/visibis.cfm

29

Example: Header information

30

Package definition and pin allocation

mysimple_buffer
signal001

12mohms

2pF

2nH

31

32

Model statement
Notice the name special_IO is assign to our single pin before.
Many pins and models can specified for single component

mysimple_buffer

signal001

12mohms

2pF

2nH

2.5pF

33

I-V curves
Construct in this

example with a spread


sheet
Break session to IBIS
Edit to view I/V curves
Assignment: Use this
example and change the
pull and pull down curves
to 15 ohms. Check with
Visual IBIS. Correct VT
waveforms.

The 4 V-t waveforms w/ spec 100ps delay

34

Match V-t and I-Curves


The intersection of the load line of the
fixture (specified in the waveform
section) and a corresponding I-V curve
determines the Voh and Voh that
should to be used in the respective V-t
Vdd
Vdd
section
Pull down

Fixture load
line
More on
load lines
later

Vol

R_fixture

Vdd

Vdd
V-t

35

End and Ramp

The ramp is specified but the simulator

tool can determine whether to use the


ramp or the V-t data
The End statement is require
The IBIS 3.1 and 2.1 are spec are actually
readable IBIS code and can be view with an
IBIS editor.

36

GTL+ on die termination


Recall that a GTL buffer contains pull-down

transistors only
No switched PMOS
Many of Intels processors and chipsets have
started to include termination devices inside the
I/O buffer.
This eliminates the stub on the PWB to connect to
the termination resistance
Vcc
On- or off-die
resistor for pull-up
and termination

37

On-die Termination

38

One way to include on-die termination is to use

superposition and add the termination currents to


the diode currents in the clamp sections.
The clamps are always active in an IBIS model,
regardless of whether the buffer is driving or
receiving. Since the termination is always active,
also, this scheme works well.
I

V
Vcc
On-die
Pull-up
Resistor

Power Clamp + On-die term.


(Put full curve into power clamp
section of IBIS model.)

Power
Clamp

Vcc

V
Vcc

Package Modeling in IBIS


Three ways to model packages in IBIS:
Lumped R, L, C values in IBIS file
Package models
EBD (Electrical Board Description)

Package models and EBDs follow this convention:

[Len=l R=r L=l C=c]


Examples:

Lumped resistor: Len=0 R=50 L=0 C=0


Capacitor package: Len=0 R=[ESR] L=[ESL] C=1uF
Package trace: Len=1.234 R=0 L=10E-9 C=2E-12

39

Example: VOL Calculation Resistor Load Line

The I-V for the resistor load is below


Vcc = 2V
50 ohms
RLoad

I
Vcc
RLOAD

Pull-down
I-V curve

50 ohm load line

Zero
Voltage

Load line
Slope = -1/RLOAD

V
VOL

Vcc

Zero Current

40

Example: VOL Calculation - buffer


Now create the NMOS I-V curve for load line
analysis below:
~10ohms

~10
I-V
I
Vcc
RLOAD

Pull-down
I-V curve

V
VOL

Vcc

41

42

Example: VOL Calculation


Using the intersection of the NMOS I-V curve and

load line, calculate VOL:


The Vol should correspond the Vol in the V-t
waveforms
Vcc = 2V
50 ohms
~10ohms

~10
I-V

50 ohms

I
Vcc
RLOAD

Pull-down
I-V curve

Sanity check and solution:


Vcc = 2V

Zero
Voltage

50 ohms
Load line
Slope = -1/RLOAD

VOL = 0.33 V

50 ohm load line


V
VOL

Vcc

Zero Current

10 ohms

Example: Calculate VOH

43

calculate VOH from the intersection of PMOS I-V

curve and the resistor load line:


The Voh should correspond to the Voh in the V-T
waveforms
Vcc = 2V

~10
I-V

~10ohms

65 ohms
30 ohms
VOH

V
VCC

Example: VOH = 1.5 V


Needs to agree with V-T data

30 ohm load line terminated


to ground this time)
I

Using IBIS Models in HSPICE

Use the IBIS file presented earlier (10 ohm


up down resistor.
Compare to
0-2V
.33ns r/f full
transition time

10

Using prior HSPICE example and MYBUF


subciruit library and switch case with alters.
New net list name: testckt_ibis.sp

44

45

Recall HSPICE Block Diagram

Printed Wiring
Board

package

package

Data generator

Buffers

Receiver

Create three libraries for MYBUF


driver source/resistor model
driver_ibis 10 ohm CMOS IBIS model

using ramp data


driver_ibis_two - 10 ohm CMOS IBIS model
2 V-t curves for rising and falling edges. (4
total)
Good example to show how to use libraries.
In some cases we start with a behavioral model
move to a transistor model to fine tune the
buffer design and solutions space.
This modularity enables this migration path with
minimal impact to the system model.

46

The three alters produces .tr0, .tr1, .tr2

Before the end statement insert the


alter statements
Adjust the pulse source to .333 ns

47

Resistor Source Library

Use delay to synchronize cases


We will force IBIS to start on the 50%
point in the bit drive waveform

48

49

HSPICE IBIS example


This is a simple

example. Many more


controls are possible
Buffer=2 tells hspice
to use an output
buffer model
Ramp_fwf and
ramp_rwf = 0 means
use the ramp
Ramp_fwf and
ramp_rwf = 2 means
use the 2 V-t curves
for each edge
The edges are scaled
by 1/10 also to match
the resistor/source
What does NINT do?

Results: first glance seem not bad

50

Closer look at rising wave

Ramp is
slightly
distorted

51

52

Closer look at falling edge

Ramp
produces
unexpected
results

Additional IBIS Modeling Information

IBIS files can be tuned to produce

desired performance
Simulator may vary on how the IBIS
files are used. Especially when the used
far away from the specified loads.

53

Bergeron Diagrams Intro.


A Bergeron diagram is another way of analyzing a transmission
line. It is useful to analyze:

Reflections from non-linear drivers or loads


Usage is in industry is low Can do same with equations and
simulators.

First example analyze a low-to-high transition:


Process
1.
2.

3.

4.
5.

6.

7.

Draw all I-V curves of transmitter and receiver


Transmission lines are load lines of 1/Zo or -1/Zo depending on
direction of wave.
Start at initial condition. For this case, it is 0V, 0A and move on
the transmission line slope to intersection of load.
Determine intersection V and I.
Create equation for transmission line with -1/Zo slope at the
intersection
Bounce back and forth using the parallel transmission line load
curves and the receiver load which is a 0v horizontal line for this
case and repeat until stable.
For this case, voltage on the load line is for Tx and a 0v is for Tx

54

Simple Bergeron Bounce Diagram Example


Why I-Vs work?

Initial Voltage Tx

Vs/R

Vs
R Pull-up
I-V curve

~R=10
I-V
Zo=50 ohm

(open)

Open
load
line

V
1) Slope
of 1/Z0

t=0

2) Slope
of -1/Z0

V at Rx

55

Determine Initial Voltage

56

Bergeron Analysis
Vs 1

let
I

V Vs
or

R
R

V
Zo

R 10 Zo 50

V 0 .1 2

f( V) Source Resistor Load Line ( M ore on f(V) late r)

First Forward Wav e Transmission Line Load Curv e


0.12
0.096
V
Zo

0.072

V Vs
0.048
R R

Zo
Vs 0.833
Zo R

0.024
0

Initial wav e looks like the


v oltage divider we e xpe ct
0

0.4

0.8

1.2

1.6

The intersection is whe re source resistor load line and


transmission line forward wav e is
Vs
V
V Vs
Solv e for V V R Zo Zo at Tx

Zo
R
R

Determine first voltage step at Rx


Now the wave continue s with as slope for -1/Zo fr om this point
The ne xt task is to dete rmine the equation of this line which has
the for m
V
I mV b -->
I
b
Zo
solve for b and substitute V and I
We can find b because we know one V,I point
Vs
b 2
Zo
Vs
R Zo
Give n
V
Vs and
I
Zo R
Zo R
V
Vs
I
2
R Zo
The open circuit r eceiv er load line is horizontal line at Zo
0 amps. This whe re the next wav e re fle cts from. So
lets solv e for V in the above for wher e I=0
0.12

0.096

Vs
Zo
R Zo

at Rx

Zo
0.072

V Vs

R R

0.048
V
Zo

Vs
RZo
0.024
0

0.4

0.8

1.2
V

1.6

Vs
Zo 1.667
R Zo

57

58

Find next voltage at Tx again


Now the wav e follows the 1/Zo I=mV+b and we solv e for b again from abov e
b

Vs

Vs

and

Vs

R Zo
Zo
R Zo
This line intersects the Tx load line
V Vs
V Vs
V
Vs
so
I

2
R
R
R
R
Zo
R Zo
3 R Zo
( R Zo)

Zo I

Vs

Zo R
( R Zo)

at Tx
2

0.08
V

0.06

Zo
0.04

V Vs

R R
V
Zo
V
Zo

0.02
Vs

Vs

( R Zo)

RZo 0.02
Vs 0.04
RZo 0.06
0.08
0.1

3 R Zo

0.4

0.8

1.2
V

1.6

Zo 1.111

59

Find voltage at Rx again


The re flected wav e follows a 1/-Zo line . Again the task is to find b. But since we know
a V and I abov e this is e asy
V
b
Zo

when I=0

4 Vs

( R Zo)

4 Vs

( R Zo)

The n

Zo

4 Vs R

V
R
4 Vs
2
Zo
( R Zo)
Zo 1
( R Zo)

at Rx

0.08
V
Zo

0.06

V Vs

R R

0.04
0.02

V
Zo

Vs
RZo

V
Vs
2
Zo
RZo

0.02

4 Vs

R
( R Zo)

Zo 0.556

0.04
V
Zo

4 Vs

R
( RZo)

2 0.06

0.08
0.1

0.4

0.8

1.2
V

1.6

And so on....

60

The non-linear case


Bergeron Analysis For Non-Linear I/V
let Vs 1

R 20 Zo 10

V 0 .01 2

2
V

2
Vs
Source I-V curv e)
Ifct( V)

R
R

V
Zo

First Forward Wave Transmission Line Load Curv e


0.12
0.096
V
Zo

0.072

Ifct ( V)0.048
0.024
0

0.4

0.8

1.2
V

Given
I0

V0
Zo

V0

2 Vs

I0

1.6
5
2

61

Use MathCad Solve blocks at Tx


-2
4.854844553088357314810
I1
2

Find( I0 V0)

V1
.48548445530883573148

I1

0.049

V1
0.485

at Tx

nee d to choose corre ct solution, look at graph


to pick

Give n ne xt line is
Given
I1

V1
b
Zo

b1 0.097

-2

b1 Find( b) 9.709689106176714629610

62

First Step at the Rx


I2 0

at the axis
Given
V2

I2

Zo

b1

V2 Find( V2) .97096891061767146296

0.12
0.096
V

V2 0.971

Zo

at Rx

0.072

Ifct ( V)
V
Zo

0.048
b1
0.024
0

0.4

0.8

1.2

1.6

I3 0

Refle cte d line


Given
I2
I3

V2
Zo
V3
Zo

b2
b2

b2 Find( b2) 9.709689106176714629610

-2

63

Assignment:
.12
V
Zo

0.12

Solve for next voltage


and current at Rx

0.096

Ifct ( V) 0.072
V
b1
Zo 0.048
V
b2
Zo
0.024
0

0
0

0.4

0.8

1.2
V

1.6

2
2

Example: Under-damped Case with Diode

64

Multiple I/V curves can be overlaid to estimate


performance

In this case an ideal diodes I-V characteristics gives a feel


for what to expect
I
20 ohms

60 ohms

Vcc = 2V
Pull-up
I-V curve

2V

1V

1/Z0

Diode
I-V curve

-1/Z0
V
Vcc

t=0

TD

2TD

3TD

4TD

5TD

6TD

Linear vs. Non-linear

65

The accuracy of a linear approximation can be


determined with a Bergeron diagram:
Voltages from the
reflections are close to
linear approximation

PMOS curve
NMOS curve

Voltages from the


reflections are NOT close
to linear approximation

1/Zo
V

1/Zo
V

Summary: We now understand

What is a model?
Importance of accurate models
Types of buffer models
IBIS and the portions of an IBIS model
How model data is generated
How to calculate VOL and VOH from a model
On-die termination
Package modeling in IBIS
Bergeron diagrams

66