Beruflich Dokumente
Kultur Dokumente
2 lectures
Prerequisite Reading Chapter 7
IBIS spec will be used as
reference
Additional Acknowledgement to Arpad Muranyi, Intel Corporation
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Additional Information
URLs
IBIS home page:
http://www.eigroup.org/ibis/ibis.htm
IBIS 3.2 spec:
http://www.vhdl.org/pub/ibis/ver3.2/
IBIS-X: http://www.eda.org/pub/ibis/futures/
Tools
Golden Parser:
http://www.eda.org/pub/ibis/ibischk3
Visual IBIS editor, SPICE-to-IBIS tool on IBIS
web site. We will use this free tool.
http://www.mentor.com/hyperlynx/visibis.cfm
Key Topics
What is a model?
Importance of accurate models
Types of buffer models
IBIS and the portions of an IBIS model
How model data is generated
How to calculate VOL and VOH from a model
Package modeling in IBIS
IBIS HSPICE example
Bergeron diagrams
What is a Model?
Intellectual
Property
Simulation
Speed
Sweep-ability
Very Little
Fast
Very
Little
Fast
Somewhat
Lots
Slowest
limited
RHigh
Linear
Models
RS
More detail
RLow
Behavioral
Models
Linear or non-linear
I-V and V-t data
Transistor
Circuit /
Netlist
Pull-down
Device
Input / Receiver
ESD Diodes
+
Inherent Diodes in Transistors
Pad Capacitance
source
V(source)
0
Time
Vlaunch
Vlaunch
A signal can be
V(load) determined by just
knowing Vlaunch,
rload, and rsource plus
0
delay
load
N ps
Vlaunch rload
Vlaunch(1+rload)
2N ps
Time
Vlaunch rloadrsource
Vlaunch(1+rload +rload rsource)
3N ps
Vlaunch r2loadrsource
Vlaunch(1+rload+r2loadrsource+ r2loadr2source)
4N ps
Vlaunch r2loadr2source
V(load)
V(source) Zo
Vs
Rs
TD = N ps
Vs
Rt
5N ps
10
Vs
ZL
ZL Z0
rload
ZL Z0
ZL Z0
and
ZL
and
Zload ( V I)
ZS
then
Vintial
Zload ( V I)
Vs
r
Zload ( V I) Z0 load
ZS Z0
ZS Z0
rsource
Zsource ( V I)
then
Zload ( V I) Z0
Zload ( V I) Z0
rsource
Zsource ( V I) Z0
Zsource ( V I) Z0
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12
13
Key
areas
of
spec
14
ESD Diodes
+
Inherent Diodes in Transistors
Output / Driver
Vcc
Pull-up
Device
I(V)
V(t)
I(V)
I(V)
V(t)
I(V)
Pull-down
Device
Vss may
be 0V
Input / Receiver
P
a
c
k
a
g
e
P
a
c
k
a
g
e
Die Pad Capacitance
Vcc
I(V)
I(V)
Vss may
be 0V
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Source
VT
Gate
Drain
Drain
Gate
Vcc
+
VGS
-
ID
Source
ID
Triode
(Ohmic)
time
0 1 2 3 4 5
VDS =
VOUT
Saturation
t=3
t=4
t=5
Vss
t=2
VCC
t=0, t=1
(no current
below Vt)
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+I
Driving
LOW
(N-channel
curve)
Pull-up
Device
on
Pull-down
Device
off
Sweep V
Vcc to 2Vcc
Output / Driver
I(V)
V(t)
I(V)
I(V)
V(t)
I(V)
Current is
positive above
Vss per
definition if I
flows
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Tristate
Sweep V
Vcc to 2Vcc
Output / Driver
Pull-up
Device
on
Pull-down
Device
off
I(V)
V(t)
I(V)
I(V)
V(t)
I(V)
Current is
negative below
Vss per
definition if I
flows
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+I
V
Vcc
Sweep V
Vcc to 2Vcc
(P-channel
curve)
Output / Driver
Pull-up
Device
on
I(V)
V(t)
I(V)
V(t)
Pull-down
Device
off
I(V)
I(V)
Current is
negative below
Vcc per definition
if I flows.
It is desirable to
make the curve
referenced to
Vcc. Will explain
later
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Power
Clamp
V
+I
Tristate
Sweep V
Vcc to 2Vcc
Output / Driver
Pull-up
Device
on
Pull-down
Device
off
I(V)
V(t)
I(V)
I(V)
V(t)
I(V)
Current is
positive above
Vcc per
definition if I
flows
It is desirable to
make the curve
referenced to Vcc.
Will explain next
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I(V)
V(t)
I(V)
V(t)
I(V)
I(V)
V(t)
I(V)
Pull up
measurement
I(V)
I(V)
V(t)
I(V)
I(V)
I(V)
Power
Clamp
V
Vcc
I(V)
V(t)
Vcc
I
Vcc
Pull up
curve
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IBIS Curve
I
Vcc
Vcc
Driving
HIGH
Vcc
Pull-up
Pull-up
Sweep V
Vcc to 2Vcc
+I
Power
Clamp
Power
Clamp
V
I
V
I(V)
V(t)
I(V)
V(t)
I-V
Controls V(t)
for High Curve
Controls V(t)
for Low Curve
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23
VCC
VOH
VCC
VOH
Driver
RLOAD
(typically 50 ohms)
t
Pull-down V-t
Measurement or Simulation Setup
VCC
VCC
Vcc
RLOAD
(typically 50 ohms)
VOL
Driver
VOL
t
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PMOS is
completely ON
PMOS begins
turning OFF
NMOS begins
turning ON
VCC
VOH
VOL
NMOS begins
turning OFF
PMOS begins
turning ON
PMOS is
completely OFF
NMOS is
completely ON
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PVT Corners
PVT = Process, Voltage, Temperature
Models in the past have historically been built at the
corners. All buffer characteristics are considered
dependent parameters with respect to PVT.
Fast Corner = Fast process, high voltage, low temp.
Slow Corner = Slow process, low voltage, high temp.
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27
Envelope.
All measured curves should
fall within these specs.
Strong
Weak
Key point!!!:
These spec curves can be
given to I/O designers to
describe required buffer
behavior.
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Envelope.
All measured curves should
fall within these specs.
Strong
Instantaneously
a short
Weak
Instantaneously
an open
Non-monotonic
Vcc = 2.0 V
Measurement threshold = 1 V; VIL = 0.8 V; VIH = 1.2 V
NMOS RON = 10 ohms
PMOS RON = 10 ohms
All edge rates are ramps of 2 V/ns
Capacitance at the die pad of the buffer = 2.5 pF
Clamps are 1 ohms and start 0.6V above and below rails
PMOS starts turning on 100 ps after NMOS starts turning
off (rising edge)
NMOS starts turning on 100 ps after PMOS starts turning
off (falling edge)
http://www.mentor.com/hyperlynx/visibis.cfm
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30
mysimple_buffer
signal001
12mohms
2pF
2nH
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32
Model statement
Notice the name special_IO is assign to our single pin before.
Many pins and models can specified for single component
mysimple_buffer
signal001
12mohms
2pF
2nH
2.5pF
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I-V curves
Construct in this
34
Fixture load
line
More on
load lines
later
Vol
R_fixture
Vdd
Vdd
V-t
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36
transistors only
No switched PMOS
Many of Intels processors and chipsets have
started to include termination devices inside the
I/O buffer.
This eliminates the stub on the PWB to connect to
the termination resistance
Vcc
On- or off-die
resistor for pull-up
and termination
37
On-die Termination
38
V
Vcc
On-die
Pull-up
Resistor
Power
Clamp
Vcc
V
Vcc
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I
Vcc
RLOAD
Pull-down
I-V curve
Zero
Voltage
Load line
Slope = -1/RLOAD
V
VOL
Vcc
Zero Current
40
~10
I-V
I
Vcc
RLOAD
Pull-down
I-V curve
V
VOL
Vcc
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42
~10
I-V
50 ohms
I
Vcc
RLOAD
Pull-down
I-V curve
Zero
Voltage
50 ohms
Load line
Slope = -1/RLOAD
VOL = 0.33 V
Vcc
Zero Current
10 ohms
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~10
I-V
~10ohms
65 ohms
30 ohms
VOH
V
VCC
10
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45
Printed Wiring
Board
package
package
Data generator
Buffers
Receiver
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48
49
50
Ramp is
slightly
distorted
51
52
Ramp
produces
unexpected
results
desired performance
Simulator may vary on how the IBIS
files are used. Especially when the used
far away from the specified loads.
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3.
4.
5.
6.
7.
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Initial Voltage Tx
Vs/R
Vs
R Pull-up
I-V curve
~R=10
I-V
Zo=50 ohm
(open)
Open
load
line
V
1) Slope
of 1/Z0
t=0
2) Slope
of -1/Z0
V at Rx
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Bergeron Analysis
Vs 1
let
I
V Vs
or
R
R
V
Zo
R 10 Zo 50
V 0 .1 2
0.072
V Vs
0.048
R R
Zo
Vs 0.833
Zo R
0.024
0
0.4
0.8
1.2
1.6
Zo
R
R
0.096
Vs
Zo
R Zo
at Rx
Zo
0.072
V Vs
R R
0.048
V
Zo
Vs
RZo
0.024
0
0.4
0.8
1.2
V
1.6
Vs
Zo 1.667
R Zo
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58
Vs
Vs
and
Vs
R Zo
Zo
R Zo
This line intersects the Tx load line
V Vs
V Vs
V
Vs
so
I
2
R
R
R
R
Zo
R Zo
3 R Zo
( R Zo)
Zo I
Vs
Zo R
( R Zo)
at Tx
2
0.08
V
0.06
Zo
0.04
V Vs
R R
V
Zo
V
Zo
0.02
Vs
Vs
( R Zo)
RZo 0.02
Vs 0.04
RZo 0.06
0.08
0.1
3 R Zo
0.4
0.8
1.2
V
1.6
Zo 1.111
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when I=0
4 Vs
( R Zo)
4 Vs
( R Zo)
The n
Zo
4 Vs R
V
R
4 Vs
2
Zo
( R Zo)
Zo 1
( R Zo)
at Rx
0.08
V
Zo
0.06
V Vs
R R
0.04
0.02
V
Zo
Vs
RZo
V
Vs
2
Zo
RZo
0.02
4 Vs
R
( R Zo)
Zo 0.556
0.04
V
Zo
4 Vs
R
( RZo)
2 0.06
0.08
0.1
0.4
0.8
1.2
V
1.6
And so on....
60
R 20 Zo 10
V 0 .01 2
2
V
2
Vs
Source I-V curv e)
Ifct( V)
R
R
V
Zo
0.072
Ifct ( V)0.048
0.024
0
0.4
0.8
1.2
V
Given
I0
V0
Zo
V0
2 Vs
I0
1.6
5
2
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Find( I0 V0)
V1
.48548445530883573148
I1
0.049
V1
0.485
at Tx
Give n ne xt line is
Given
I1
V1
b
Zo
b1 0.097
-2
b1 Find( b) 9.709689106176714629610
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at the axis
Given
V2
I2
Zo
b1
0.12
0.096
V
V2 0.971
Zo
at Rx
0.072
Ifct ( V)
V
Zo
0.048
b1
0.024
0
0.4
0.8
1.2
1.6
I3 0
V2
Zo
V3
Zo
b2
b2
-2
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Assignment:
.12
V
Zo
0.12
0.096
Ifct ( V) 0.072
V
b1
Zo 0.048
V
b2
Zo
0.024
0
0
0
0.4
0.8
1.2
V
1.6
2
2
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60 ohms
Vcc = 2V
Pull-up
I-V curve
2V
1V
1/Z0
Diode
I-V curve
-1/Z0
V
Vcc
t=0
TD
2TD
3TD
4TD
5TD
6TD
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PMOS curve
NMOS curve
1/Zo
V
1/Zo
V
What is a model?
Importance of accurate models
Types of buffer models
IBIS and the portions of an IBIS model
How model data is generated
How to calculate VOL and VOH from a model
On-die termination
Package modeling in IBIS
Bergeron diagrams
66