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A Digital Circuit, in general, can be subdivided into two

parts:

Combinational part A circuit whose output is a function of its

current inputs only

Sequential part A circuit whose output is a function of its current

inputs plus the past inputs [requires memory elements such as latches

or flip-flops]

A System - comprising of inputs, outputs, and states while modeling

time as discrete instants at which inputs or outputs can change

Synchronous FSM when states and output transitions are

synchronized with a clock (positive or negative edge)

Asynchronous FSM - when states and output transitions can occur

at any time in response to input changes

NDG on FSM

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

FSM Models

Mealy Model Contains three components:

State Memory to store the current state S(t)

State Transition Function to determine the next state

S(t+1) depending upon the current state S(t) and the input X(t)

Output Function which generates the output Y(t) as

function of the current state S(t) and the input X(t)

NDG on FSM

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

Moore Model Similar to Mealy Model except that Output

Function which generates the output Y(t) as function of the

current state S(t) only.

Both Mealy and Moore Models can be mapped into each other

Mealy Machines usually have fewer state variables (memory

elements)- Widely used in Engineering Applications

Moore Machines are simpler to analyze mathematically

NDG on FSM

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

A Problem with Mealy Machine (as shown in Fig-01)

Output may have glitches. So, a slightly modified version of

Mealy Machine is more commonly used.

FSMs ?

NDG on FSM

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

Autonomous FSM Special FSM having no inputs, e.g. LFSR

Communicating FSMs Two or more FSMs interacting with

each other

NDG on FSM

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

1. Understand the Specifications

2. Problem Definition Using State Diagram and/or State Table

3. State Minimization Removal of redundant internal states

4. State Assignment Assigning binary codes to the states

5. Determination of State Transition Function and Output

Function Equations

6. Logic Equation Minimization

7. Design Mapping to a given Technology or Device

but not necessary steps

NDG on FSM

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

Step-1: Understanding the Specifications

A Simple Vending Machine Design Example: [a] Accepts 1 or 2

Rupees Coins [b] Delivers a Pak-Cola bottle of drink costing

Rupees 3 [c] Provides change where applicable

Rs. 1 Coin

Vend

COINS

Input Conditioning

Output

Drivers

FSM

Rs. 2 Coin

Drink / Change

Change

CLOCK

Fig-05: A Vending Machine Model

NDG on FSM

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

Contd

Step-2: State Diagram

Representation

Each State is represented as a circle

with output arrows

Inputs: Rs. 1: Rs. 2 00/00 Outputs: Vend: Change

Next to the arrow, input and outputs

are given

For Vending Machine, FSM remains in

state S0 until there is some coin, either

State Name

of Rs. 1 or Rs. 2 inserted.

S0

Upon such an event, depending upon

Idle

the coin type, it switches to another state

Description

FSM should not activate the Vend /

Change driver unless the credit equals or

10/00

01/00

exceed the Rs. 3

A state transition diagram can be

Fig-06: Notation used in State Diagram Representation

drawn as shown in Fig-07(Next Slide)

NDG on FSM

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

Step-2: State Diagram Representation Let us Complete it

Inputs/Outputs = Rs.2:Rs.1/Vend:Change

S0

S1

S3

S7

S2

S4

S5

S6

S8

NDG on FSM

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

Step-3: State Minimization

Equivalent States: Two states are said to be equivalent if they

have identical next states and outputs.

00/00

00/00

Inputs/Outputs=

Rs.2:Rs.1/Vend:Change

Reset

S0

Reset

S0

00/00

00/00

00/00

00/00

01/10

01/00

S2

S2

10/10

10/11

00/00

S1

10/00

01/00

S1

S3

[a]

[b]

Fig-08: State Minimization Step-03 [a] Cyclic State Diagram of VM [b] Reduced FSM for VM

NDG on FSM

10

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

Step-3: State Minimization Contd

Addition of Invalid State(s) due to State Assignment (Binary Codes)

00/00

Inputs/Outputs=

Rs.2:Rs.1/Vend:Change

S0

00/00

S3

xx/00

00/00

01/10

01/00

S2

10/10

S1

10/00

10/11

01/00

NDG on FSM

11

Step-4: State Assignment and State Transition Table

Table-01: State Transition Table for Vending Machine

Current State

Inputs = Rs.2:Rs.1

Next State

Outputs= Vend:Change

S0

S0

S0

S1

S1

S1

S2

S2

S2

S3

00

01

10

00

01

10

00

01

10

XX

S0

S1

S2

S1

S2

S0

S2

S0

S0

S0

00

00

00

00

00

10

00

10

11

00

Current State

NDG on FSM

S0

S1

S2

S3

00

S0, 00

S1, 00

S2, 00

S0, 00

01

11

S1, 00

S0, 00

S2, 00

S0, 00

S0, 10

S0, 00

S0, 00

S0, 00

10

S2, 00

S0, 10

S0, 11

S0, 00

12

Step-4: State Assignment and State Transition Table

Table-02: Compact State Transition Table for VM

Current State

S0

S1

S2

S3

00

S0, 00

S1, 00

S2, 00

S0, 00

01

11

S1, 00

S0, 00

S2, 00

S0, 00

S0, 10

S0, 00

S0, 00

S0, 00

10

S2, 00

S0, 10

S0, 11

S0, 00

00

01

10

11

00

00, 00

01, 00

10, 00

00, 00

01

11

01, 00

00, 00

10, 00

00, 00

00, 10

00, 00

00, 00

00, 00

10

10, 00

00, 10

00, 11

00, 00

s1(next) = /s1*/s0*Rs.2*/Rs.1 + /s1*s0*/Rs.2*Rs.1 + s1*/s0*/Rs.2*/Rs.1

s0(next) = /s1*/s0*/Rs.2*Rs.1 + /s1*s0*/Rs.2*/Rs.1

Change = s1*/s0*Rs.2*/Rs.1

NDG on FSM

13

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

Step-6-7: Simplification of Logic Equations and

Hardware Implementation

Use of K Maps or Other Methods

Implementation is Technology Dependent

Clock

Rs. 2

Rs. 1

Vend

Combinational Logic

Gates

Change

NDG on FSM

14

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

Used for JPEG/MPEG Compression

Relies on known probability of a set of fixed symbols

Binary Code and Frequency

NDG on FSM

15

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

Huffman Decoder Circuit Implementation as FSM

NDG on FSM

16

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

FSM Optimization

Three Ways to Optimize the HW Complexity of FSM

State Minimization

State Assignment

Logic Equation Minimization

State Merging by Observation

State Partitioning

Application of Implication Tables

Vending Machine Example

Bit Sequence Detector

NDG on FSM

17

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

State Merging by Observation

Bit Sequence Detector A Circuit that generates an output

Z = 1 when it detects a bit sequence from a serial data input D

as 001, 010, 100, or 111.

Fig-12: Bit Sequence Detector [a] State Diagram [b] State Table

Eliminate S5 and S6

NDG on FSM

18

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

State Merging by Observation Contd

Bit Sequence Detector after State Minimization

Fig-13: Minimal State Bit Sequence Detector [a] Stat Table [b] State Diagram

NDG on FSM

19

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

State Partitioning

An FSM Example

Partitioning Example

NDG on FSM

20

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

State Partitioning Contd

An FSM Example

Step-1: State Partitioning by Outputs Divide the states into

sets with identical outputs

each set, find their next states separately

NDG on FSM

0 and 1, do not belong to any

other single set of states

FPGA Based System Design

21

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

State Partitioning Contd

An FSM Example

Step-3: Repartitioning based on Next States After Step-2, two

things have happened: next state group for C (input = 0) now belongs to

B2, however, next state group for A (input = 1) now belongs to no single

state group, so, A partition has become invalid

to some single state partition/group.

WHAT is Final Partitioning ?

NDG on FSM

22

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

State Partitioning Contd

An FSM Example

Finally We got a State Partitioning Where

Next outputs are the same for each state in the same state

partition/group

AND

Next states are the same for each state in the same

set/group

Final Optimized FSM has got only

Five States.!

NDG on FSM

23

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

Implication Table: Easy to Computerize

and Suitable for Larger FSM

Optimization

NDG on FSM

24

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

State Assignment

Assigning Unique Binary Codes to the States of a Minimized

FSM

State Minimization has a Unique Technology-Independent

Solution, however, State Assignment Depends on

Technology such as PLA, ROM, PAL, logic gates

Type of storage circuit, D-latches or FF

Possible Permutations are

N = 2n ! / (2n-r)!

Many, among above Assignments, are just Rearrangements,

according to McCluskey, Number of Distinct Assignments is

Reduced to

ND = (2n -1)! / (2n-r)!* n!

NDG on FSM

25

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

State Assignment Contd

Even the number given by McCluskey is still very large

Such a problem usually have no optimal solution but some

solution based on heuristics (thumb rules or simple rules)

number of 1s in adjacent cells of next-state truth table for

better k-map reduction

NDG on FSM

26

FSM Optimization Contd

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

Rule-1: States with the same next state for a given input

condition should be assigned codes differing in one (binary) bit

position only. For Example,

adjacent state assignments. For Example,

NDG on FSM

27

FSM Optimization Contd

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

Example-01: Consider the Bit Sequence Detector FSM

adjacent codes, so, let S1 = 100 and S2 = 101

Applying Rule 1, S3 and S4 both have the same next state with

given input condition, so, S3 and S4 are assigned logically

adjacent codes. S3 = 110 and S4 = 111

S0 can be assigned 000 (arbitrary), and unassigned states would

be 010, 011, and 001

NDG on FSM

28

FSM Optimization Contd

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

One-Hot State Assignment

Sometimes, instead of log2 r bi-stable latches, it is more

efficient (and convenient as well ) to have r latches/flip-flops,

i.e. one for each state. It is called One-Hot State Assignment.

At any time, only one FF will be set (FF corresponding to

the state where FSM lies at that instant)

No State Assignment is required

One-hot state assignment is particularly suitable for FPGA

(LUT and MUX based Architecture) implementation of FSM

State Encoding

Slower in Operation as compared to other option.

NDG on FSM

29

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

Fig-16:

Generic Block

Diagram of

FSM

Implementation Alternatives

Standard ICs Suitable for Simple Designs

PROM Suitable for many Outputs/States, No Logic Minimization needed,

Exhaustive Implementation for all Possible Input Combinations, Size grows

Exponentially

Fig-17:

Implementation of

FSM with PROM

NDG on FSM

30

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

Fig-18:

Asynchronous

Inputs to FSM

Asynchronous input A to FSM, while making transition from 0 to

1, as shown above may give rise to a wrong state transition

SOLUTION: Synchronize all the Asynchronous Inputs to FSM using a

Latch clocked by the FSM clock

Fig-19:

Synchronizing

Asynchronous

Inputs

NDG on FSM

31

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

Types of Flip-Flops at Output

Outputs of Programmable Macro-Cells or LEs of CPLDs/FPGAs

are Configurable

Inverting/Non-Inverting

Register or Combinational

D Flip-Flop, S-R FF, J-K FF, or T-FF, any type is Possible

T-FF or J-K FF can Produce more Efficient Implementation

(fewer product terms in Boolean Equations)

Better CAD tools make better choice automatically

NDG on FSM

32

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

An Alternative Method to Represent FSM based on FlowChart Notation Popularized by Christopher Clare Designing

Logic Systems Using State Machines

[a]

time (Clock Cycle)

Single Entry Point for each State

Block

For each combination of inputs,

only one unambiguous exit path

Outputs asserted high, low, highimpedance until the next clock cycle

NDG on FSM

[b]

Fig-20: ASM Chart [a] ASM Elements [b]

An ASM Block

33

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

ASM Construction Rules

Must Follow these Rules:

Each State can have one and only

one State Box

Outputs depending on the Current

State only (Moore Model) are

represented by Square Box

Outputs depending on the Inputs

(and of course the Current State), as

in Mealy Model, are represented by

Rounded Box

Decision Box contains the

Conditions for the Input Variables

NDG on FSM

Simplification

34

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

ASM Advantages over (Bubble) State Diagram

ASM Chart reflects HW Algorithm

better than (Bubble) State Diagram

Representation of FSM

Easier to Follow and Understand

ASM Chart avoids Transition

Conflicts that could Occur in State

Diagram Representation of FSM

EXAMPLE: Inputs I3I2I1I0 = 1101, 1011,

and 1111 all will make both transitions

to be True.

Fig-22: Possible Conflicts in State

Diagram Representation of an FSM

NDG on FSM

35

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

ASM Representation of Vending Machine

Rs.0

00/00

S0

00/00

00/00

01/10

01/00

Rs.1

Rs.1

Rs.2

Rs.1

10/00

S2

10/10

S1

Rs.2

Inputs/Outputs=

Rs.2:Rs.1/Vend:Change

S3

xx/00

Rs.2

10/11

01/00

[a]

Rs.1

Rs.2

[b]

Fig-23: Mealy Model of Vending Machine [a] State Diagram [b] ASM Chart

NDG on FSM

36

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

Mealy FSM and Its RTL Coding

Fig-24: Mealy FSM to

be Coded in Verilog

HDL

NDG on FSM

37

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

Mealy FSM and Its RTL Coding Contd

NDG on FSM

38

Mealy FSM and Its RTL Coding Contd

Contd from Prev. Slide

NDG on FSM

39

Mealy FSM and Its RTL Coding Contd

Contd from Prev. Slide

NDG on FSM

40

Mealy FSM and Its RTL Coding Contd

Contd from Prev. Slide

NDG on FSM

41

* Chapter # 5 and Peter Cheung Lecture Notes-DSD-06

Moore FSM and Its RTL Coding

NDG on FSM

42

Moore FSM and Its RTL Coding

Contd from Prev. Slide

NDG on FSM

43

Moore FSM and Its RTL Coding

Contd from Prev. Slide

NDG on FSM

44

Moore FSM and Its RTL Coding

Contd from Prev. Slide

NDG on FSM

45

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