Sequential Circuits: Boonchuay Supmonchai

Chapter 7
Sequential Circuits
Boonchuay Supmonchai
Integrated Design Application Research (IDAR) Laboratory
August 20, 2004; Revised - July 4, 2005
B.Supmonchai
Goals of This Chapter
Implementation techniques for

Register: latches and flipflops
Schmitt Triggers
Oscillator, pulse generators
Static versus Dynamic Realization
Clocking Strategies
2102-545 Digital ICs
Sequential Logic
B.Supmonchai
Sequential Logic
Inputs
Outputs
COMBINATIONAL
LOGIC
Current State
Next state
Q
State
Register
CLOCK
Storage Mechanisms
Positive Feedback
STATIC
Charge-Based
DYNAMIC
Sequential Logic
B.Supmonchai
Static vs Dynamic Storage
Static storage
preserve state as long as the power is on
have positive feedback (regeneration) with an internal
connection between the output and the input

useful when updates are infrequent (clock gating)
Dynamic storage
store state on parasitic capacitors
only hold state for short periods of time (milliseconds)
require periodic refresh

usually simpler, so higher speed and lower power
Sequential Logic
B.Supmonchai
Latches versus Flipflops
Latches (with Clock)

level sensitive circuit that passes inputs to Q when the clock is
high (or low) - transparent mode

input sampled on the falling edge of the clock is held stable
when clock is low (or high) - hold mode
Flipflops (edge-triggered)
edge sensitive circuits that sample the inputs on a clock
transition
positive edge-triggered: 0 1
negative edge-triggered: 1 0
built using latches (e.g., master-slave flipflops)
Sequential Logic
B.Supmonchai
Review: The Regenerative Property

Vi1
Vo1
Vi2
Vo2
Small deviation from

bias point C (e.g., from
noise) is amplified and
regenerated around the
circuit loop until either
point A or B is reached
If the gain in the

transient region is larger
than 1, only A and B are
stable operation points.
C is a metastable
operation point.
Cascaded Inverters
A
C
B
Vi1 = Vo2
Sequential Logic
B.Supmonchai
Review: Bistable Circuits
The cross-coupling of two

inverters results in a
bistable circuit (a circuit
with two stable states)
Vi1
Vi2
Have to be able to change the stored value by making A

(or B) temporarily unstable by increasing the loop gain
to a value larger than 1
done by applying a trigger pulse at Vi1 or Vi2
the width of the trigger pulse need be only a little larger than
the total propagation delay around the loop circuit (twice the
delay of an inverter)
Sequential Logic
B.Supmonchai
Review: SR Latch
!Q
!Q
Action
!Q
memory
set
reset
disallowed
Sequential Logic
B.Supmonchai
Review: Clocked D Latch

D
!Q
clock
clock
transparent mode
In our course
All latches mean
clocked latches
clock
hold mode
Sequential Logic
B.Supmonchai
Latches versus Flipflops II
Latch
stores data when

clock is low (high)
stores data when

clock rises (falls)
D Q
D Q
Clk
Clk
Clk
Clk
Flipflop
Sequential Logic
10
B.Supmonchai
Positive and Negative Latches

Positive Latch
In
Negative Latch
In
Out
Clk
Clk
Clk
Clk
In
In
Out
Out
Out
Stable
Out
Follow In
Out
Stable
Out
Follow In
Sequential Logic
Out
Stable
Out
Follow In
Out
Out
Stable
Out
Follow In
11
B.Supmonchai
Latch-Based Design
N latch is transparent
when f = 0
P latch is transparent
when f = 1
N
Latch
Logic
P
Latch
Logic
Sequential Logic
12
B.Supmonchai
Timing Metrics
clock
clock
tsu
In
time
thold
data
stable
time
tc-q
Out
output
stable
output
stable
time
Sequential Logic
13
B.Supmonchai
Timing Definitions
Setup time, tsetup is the time that the data inputs

(D) must be valid before the clock transition
0 to 1 transition for a positive edge-triggered device
1 to 0 transition for a negative edge-triggered device
Hold time, thold is the time that the data inputs

must remain valid after the clock edge
Propagation Delay, tc-q is the worst case

propagation delay (with reference to the clock
edge)
time to copy D to Q
Sequential Logic
14
B.Supmonchai
System Timing Constraints

Inputs
Outputs
COMBINATIONAL
LOGIC
Current State
Next state
Q
State
Register
T (clock period)
CLOCK
tcd: contamination delay = minimum delay
tcdreg + tcdlogic thold

T tc-q + tplogic + tsu
Sequential Logic
15
B.Supmonchai
Notes on System Timing Constraints
It is important to minimize the values of the timing

parameters associated with the register.
In modern high-performance systems, the register

propagation delay and set-up times account for a
significant portion of the clock period.
DEC Alpha EV6 has a maximum logic depth of 12 gates and
the register overhead accounts for about 15% of the clock

period.
Hold time becomes an issue when there is little logic

between registers or when the clocks at different
registers are somewhat out of phase due to clock skew.
Sequential Logic
16
B.Supmonchai
Building A (Static) Latch

For a latch, use the clock as a decoupling signal, that
distinguishes between the transparent and opaque states
CLK
CLK
Q
CLK
D
CLK
CLK
Cutting the feedback loop

(Mux-based latch)
can implement as NMOS-only

Overpowering the feedback loop
(as in Static RAM)
Sequential Logic
17
B.Supmonchai
MUX Based Latches
Change the stored value by cutting the feedback loop

feedback
feedback
0
Q
clk
1
clk
Positive Latch
Negative Latch
Q = clk & Q | !clk & D
Q = !clk & Q | clk & D
transparent when the

clock is low
transparent when the

clock is high
Sequential Logic
18
B.Supmonchai
TG MUX Based Latch Implementation

clk
Positive Latch
Q
input sampled
(transparent mode)
!clk
D
clk
clk
clk load is two transistors (and two
for !clk) = clock load of 4
!clk
Having to generate both clk and !clk

(nonoverlapping clocks)
Sequential Logic
feedback
(hold mode)
19
B.Supmonchai
PT MUX Based Latch Implementation

clk
!Q
input sampled
(transparent mode)
!clk
clk
Reduced clock load, but
threshold drop at output of
pass transistors so reduced
noise margins and performance
!clk
Sequential Logic
feedback
(hold mode)
20
B.Supmonchai
Latch Race Problem

B
clk
clk
Which value of B is stored?
T tc-q + tplogic + tsu

Thigh tc-q + tcdlogic
Two-sided clock constraint

Sequential Logic
21
B.Supmonchai
Master Slave Based ET Flipflop

D
0
1
D
Q
QM
clk
clk
clk
clk
Slave
Master
clk = 0
transparent
hold
clk = 1
hold
transparent
Sequential Logic
QM
Q
22
B.Supmonchai
MS ET Implementation
Slave
Master
I2
I3
T2
I5
T4
I4
T3
I6
QM
D
I1
T1
20 Transistors*
8 clock loads
clk
* Ignore clk buffer
master transparent
slave hold
clk
master hold
slave transparent
!clk
Sequential Logic
23
B.Supmonchai
MS ET Timing Properties
Assume propagation delays are tpd_inv and tpd_tx, that the

contamination delay is 0, and that the inverter delay to
derive !clk is 0
Set-up time - time before rising edge of clk that D must

be valid
tsu = 3 * tpd_inv + tpd_tx
Propagation delay - time for QM to reach Q

tpd = tpd_inv + tpd_tx
Hold time - time D must be stable after rising edge of clk

thold = 0
Sequential Logic
24
B.Supmonchai
Notes on MS ET Timing Properties
Set-up time
How long before the rising edge does D have to be stable such
that QM samples the value reliably?

D has to propagate through I1, T1, I3 and I2 before the rising
edge to ensure that the node voltages on both terminals of T2

are the same value.
Propagation delay time

Since the delay of I2 is included in the set-up time, the output
of I4 is valid before the rising edge of clk, so the delay is

simply the delay through T3 and I6
Hold time
since T1 turns off when the clock goes high, any changes in D
after clk goes high are not seen, so hold time is 0

Sequential Logic
25
B.Supmonchai
Set-up Time Simulation

3
2.5
QM
Volts
2
1.5
1
tsetup = 0.21 ns
clk
0.5
I2 out
-0.5
0
0.2
0.4
0.6
0.8
Time (ns)
works correctly
Sequential Logic
26
B.Supmonchai
Set-up Time Simulation II

3
2.5
I2 out
Volts
2
1.5
1
tsetup = 0.20 ns
clk
0.5
QM
-0.5
0
0.2
0.4
0.6
0.8
Time (ns)
Fails!
the clock is enabled before the nodes on both sides

of the transmission gate T2 settle to the same value
Sequential Logic
27
B.Supmonchai
Propagation Delay Simulation

tc-q (LH) = 160 psec
tc-q (HL) = 180 psec
2.5
Volts
Clk
1.5
tc-q (LH)
tc-q (HL)
0.5
0
-0.5
0.5
1.5
2.5
Time (ns)
propagation delay is measured from the 50% point
of the clk edge to the 50% point of the Q output
Sequential Logic
28
B.Supmonchai
Reduced Load MS ET FF
Clock load per register is important since it directly

impacts the power dissipation of the clock network.
Can reduce the clock load (at the cost of robustness) by

making the circuit ratioed
I3
I1
QM
T
1
T
2
I2
!clk
12 Transistors
4 clock loads
!clk
clk
clk
Q
I4
reverse conduction
to switch the state of the master, T1 must be sized to overpower I2

to avoid reverse conduction, I4 must be weaker than I1
Sequential Logic
29
B.Supmonchai
Non-Ideal Clocks
Clk and !clk are never perfect inversions of one another

We must generate !clk and route both signals
Variations can exist in the wires used to route the two clock
signals and load capacitances may vary
Non-ideal clocks create skew resulting in clock overlap

1-1 Overlap
clk
clk
!clk
!clk
Ideal clocks
0-0 Overlap
Non-Ideal clocks
Sequential Logic
30
B.Supmonchai
Example of Clock Skew Problems

X
clk
!clk
Race
D
P1
I2
I1
P3
I3
I4
P2
P4
!clk
clk
!Q
Race condition direct path from D to Q during the short time

when both clk and !clk are high (1-1 overlap)
Undefined state both B and D are driving A when clk and !clk
are both high
Dynamic storage when clk and !clk are both low (0-0 overlap)
Sequential Logic
31
B.Supmonchai
Pseudostatic Two-Phase ET FF
X
clk1
D
P1
I2
I1
P3
B
P2
clk2
master transparent
slave hold
clk1
clk2
dynamic
storage
tnon_overlap
I3
I4
!Q
P4
clk1
master hold
slave transparent
clk2
Sequential Logic
32
B.Supmonchai
Two Phase Clock Generator

A
clk1
clk
B
clk2
clk
A
B
clk1
clk2
Sequential Logic
33
B.Supmonchai
Power PC Flipflop
!clk
clk
1D
01
!clk
10
10
clk
master transparent
slave hold
clk
16 Transistors
8 clock loads
master hold
slave transparent
!clk
Q 01
Sequential Logic
34
B.Supmonchai
Overpowering The Feedback Loop

Clocked SR Latch
Cross-coupled NANDs
S
M2
M4
Q
!Q
clk
M6
M1
M8
clk
M7
M3
M5
This is not used in datapaths any more,

but is a basic building block for memory cell
Sequential Logic
35
B.Supmonchai
Ratioed CMOS Clocked SR Latch

off on
on off
M2
M4
Q 1 0
1 0 !Q
off ->on
0 1 clk
off ->on
M6
M1
0 S
on off
clk 0 1
M7
R 1
M3
off on
M5
on
off
M8
8 Transistors
2 Clock loads*
* sized
No static power consumption, but a ratioed device

where sizing is critical to ensure proper functionality
M7, M8 must overcome M4 to bring Q low, so must M5, M6
over M2
Sequential Logic
36
B.Supmonchai
Sizing Issues
(W/L)2 and 4 = 1.5m/0.25 m
(W/L)1 and 3 = 0.5m/0.25 m
!Q (Volts)
1.5
so (W/L)5 and 6 > 3
0.5
0
2
2.5
3.5
(W/L)5 and 6
Output voltage depends on pull-down transistor width

Sequential Logic
37
B.Supmonchai
Transient Response
!Q (Volts)
!Q
S
W=0.5 m
W=0.6 m
W=0.7 m
W=0.8 m
W=1 m
W=0.9 m
0
0
0.4
0.8
1.2
1.6
Time (ns)
Individual device ratio for M5 or M6 must be larger than approx. 6.
Analysis results give 2.26 (instead of 3) since it doesnt take into account
channel length modulation and DIBL (drain induced barrier loading).
Sequential Logic
38
B.Supmonchai
6 Transistor CMOS SR Latch

clk
clk
Problems with noise

margins and static
power consumption
due to threshold drop
across pass transistors
Once again, sizing is

important - especially
M5 and M6
clk
clk
M2
M4
Q
R
M5
!Q
M1
M6
M3
6 Transistors
2 Clock loads
Sequential Logic
39
B.Supmonchai
Review: Storage Mechanisms

Dynamic
(charge-based)
Static
(Positive Feedback)
CLK
CLK
Q
CLK
D
CLK
CLK
Useful when update is infrequent

Simpler, Faster, and Lower Power
Sequential Logic
40
B.Supmonchai
Dynamic ET Flipflop
master
slave
!clk
clk
T1
I1
QM
T2
C
1
clk
I2
C
!clk
tsu = tpd_tx
thold = zero
tc-q = 2 tpd_inv + tpd_tx
master transparent
slave hold
clk
!clk
8 Transistors
4 Clock loads
master hold
slave transparent
Sequential Logic
41
B.Supmonchai
Dynamic ET FF Race Conditions

!clk
clk
QM
T1
I1
T2
C
clk
clk
!clk
I2
C
!clk
0-0 overlap race condition
toverlap0-0 < tT1 + tI1 + tT2

1-1 overlap race condition
toverlap1-1 < thold

Sequential Logic
42
B.Supmonchai
Dynamic Two-Phase ET FF
clk1
clk2
QM
T1
T2
I1
C
!clk1
I2
!clk2
master transparent
slave hold
clk1
tnon_overlap
clk2
master hold
slave transparent
Sequential Logic
43
B.Supmonchai
Pseudostatic Dynamic Latch
Robustness considerations limit the use of dynamic FFs

Coupling between signal nets and internal storage nodes can
inject significant noise and destroy the FF state

Leakage currents cause state to leak away with time
Internal dynamic nodes dont track fluctuations in VDD that
reduces noise margins
A simple fix is to make the circuit pseudostatic

clk
Slight increase in delay

(adds to the capacitive
load) and power
consumption, but it
improves noise immunity
significantly
T1
!clk
Sequential Logic
44
B.Supmonchai
C2MOS (Clocked CMOS) ET Flipflop

Master
Slave
M2
on
clk
M4
off
on
M3
!clk
QM
C1
off
!clk
M8
on
off
clk
M7
Q
C2
on
off
M1
M5
master transparent
slave hold
clk
!clk
8 Transistors
4 Clock loads
M6
Insensitive to clock
overlap as long as the
rise and fall times of
the clock edges are
sufficiently small
master hold
slave transparent
Sequential Logic
45
B.Supmonchai
C2MOS FF 0-0 Overlap Case

M2
M4
D
M3
M6
QM
C1
M7
M1
C2
M5
clk
clk
!clk
!clk
M8
Sequential Logic
46
B.Supmonchai
Notes on C2MOS FF 0-0 Overlap Case
Does any new data sampled during the overlap window

propagate to Q (race)?
New data is sampled on QM, but cannot propagate to Q since
M7 is off (slave is in hold).

Any new data sampled on the falling clock edge is not seen at Q
For clocking on the left: at the end of the overlap period

!clk = 1 and both M7 and M8 turn off, putting the slave
in the hold mode
For the clocking on the right: at the end of the overlap

period clk = 1 and both M3 and M4 turn off, putting the
master in the hold mode (affects setup time as well)
The result: the FF is slower (slower tc-q time)
Sequential Logic
47
B.Supmonchai
C2MOS FF 1-1 Overlap Case

M2
M4
D
1
M3
M6
M8
QM
C1
Q
1
M1
M7
C2
M5
clk
clk
!clk
!clk
1-1 overlap constraint: toverlap1-1 < thold
Sequential Logic
48
B.Supmonchai
Notes on C2MOS FF 1-1 Overlap Case
New data is sampled on QM, but cannot propagate to Q

since M8 is off (slave is in hold).
A bit more problematic than 0-0 overlap.

It must enforce a hold time on D, so that changing D which
reaches QM is not copied to Q when overlap time is over
first clocking condition.

By imposing a hold time on D - that D must be stable during
clock overlap - overcome this problem as well
However, possible race can occur if the rise/fall times of

the clock are sufficiently slow.
Works correctly as long as the clock rise/fall times is smaller
than approximately five times the propagation delay of the

flipflop.
Sequential Logic
49
B.Supmonchai
C2MOS Transient Response

3
QM(3)
2.5
Q(3)
2
1.5
Q(0.1)
clk(0.1 ns)
0.5
clk(3 ns)
0
-0.5
0
Time (nsec)
For slow clocks, potential for a race condition exists

Sequential Logic
50
B.Supmonchai
True Single Phase Clocked (TSPC) Latches

Negative Latch
Positive Latch
Q
clk
In
clk
In
hold when clk = 1

transparent when clk = 0
clk
clk

hold when clk = 0
Uses only a single clock

No clock overlap (skew) to worry about ; reduced clock load
Sequential Logic
51
B.Supmonchai
Embedding Logic in TSPC Latch

A
PUN
Q
In
clk
clk
Q
clk
clk
PDN
B
A AND B
Logic can be embedded into latch (or FF)

Reduce delay overhead associated with the latch
Sequential Logic
52
B.Supmonchai
Notes on Embedding Logic in TSPC Latch
Set-up time increased, but overall performance

improved
The increase in the set-up time is typically smaller than the
delay of an AND gate.

For example, using minimum size devices set-up of AND
latch is 140 psec.

Using the conventional approach of AND gate followed by
latch has an effective set-up time of 600 psec.
Technique used extensively in the design of the EV4

DEC Alpha microprocessor and many other high
performance processors.
Sequential Logic
53
B.Supmonchai
TSPC ET FF
Master
clk
on
off
clk
Slave
on
QM
off
on
clk off
on
clk
Q
off
12 Transistors
4 Clock loads
master transparent
slave hold
master hold
slave transparent
clk
Virtually all constraints removed - no clocks to overlap, no race

Sequential Logic
54
B.Supmonchai
Notes on TSPC ET FF
Warning! - similar to C2MOS, TSPC flipflops

malfunction when the slope of the clock is not
sufficiently steep.
Slow clock cause both the NMOS and PMOS
clocked transistors to be ON simultaneously,

resulting in undefined values of the states and race
conditions.
Clock slopes thus must be carefully engineered. If
necessary, local buffers must be introduced to ensure

the quality of the clock signal
Sequential Logic
55
B.Supmonchai
Simplified TSPC ET FF
I1
clk
I3
off
on
M6
M9
Y1D
clk
on X !D
clk
off M2
off
M5
on M8
clk
M1
Moff
M7
4
on
M3
I2
9 Transistors*
4 Clock loads
I1 sample (transparent)
I2 precharged
I3 hold
*(11 if Q is needed)
I1 hold
I2 evaluate
I3 sample (transparent)
clk
Q D
Sequential Logic
56
B.Supmonchai
Notes on TSPC ET FF
On the positive edge of the clock, note that the node X

transitions to a low if D is high. Therefore, the input
must be kept stable until the value on node X before the
rising edge of the clock propagates to Y
Hold time of the register (less than 1 inverter delay since it
takes 1 inverter delay for the input to affect node X).
Propagation delay is essentially three inverters since

the value on node X must propagate to output Q
Set-up time is the time for node X to be valid one
inverter delay
Sequential Logic
57
B.Supmonchai
Sizing Issues in Simplified TSPC ET FF

clk
!Qmod
Transistor sizing
!Qorig
2
Original width
M4, M5 = 0.5m
M7, M8 = 2m
Qmod Qorig
0
0
0.2
0.4
0.6
0.8
Time (nsec)
Modified width
M4, M5 = 1m
M7, M8 = 1m
Sizing is critical with improper sizing glitches may occur due

to race condition when the clock transitions from low to high
Sequential Logic
58
B.Supmonchai
Split-Output TSPC Latches

Positive Latch
Negative Latch
Q
In
clk
A
In
clk

hold when clk = 0
hold when clk = 1

When In = 0, A = VDD - VTn
When In = 1, A = | VTp |
Sequential Logic
59
B.Supmonchai
Split-Output TSPC ET FF
8 Transistors*
2 Clock loads
*(10 if Q is needed)
clk
A
clk
QM
Q
Which edge-triggered?
Downside is not all node voltages in the latch experience

full logic swing due to threshold drop.
E.g., for positive latch when D=0 and clk=1, A=Vdd-Vth (Also
limits the amount of Vdd scaling possible with this latch).

Sequential Logic
60
B.Supmonchai
Pulse-Triggered Flipflops
Another approach to design an edge-triggered

flipflop is to use pulse-triggered.
Master-Slave Flipflop
L1
Data
D
Clk
Pulse-Triggered Flipflop
L2
D
L
Q
Clk
Data
Clk
Clk
Clk
Sequential Logic
61
B.Supmonchai
Pulsed FF (AMD-K6)
Pulse registers - a short pulse (glitch clock) is generated

locally from the rising (or falling) edge of the system
clock and is used as the clock input to the flipflop
OFF
clk
0/Vdd
P1ON X Vdd
P3
M3OFF
M6OFF
ON
1/0
D
1
1/0
P2
M5
OFF
1
0
ON
M2ON/
0
ON/OFF
M1ON
!clkd
M4
ON
OFF
Sequential Logic
62
B.Supmonchai
Notes on Pulsed FF
Race conditions are avoided by keeping the transparent

mode time very short (during the pulse only)
Reduce clock load but substantially increase complexity

in verification
The transparency period determines the hold time.

The window must be wide enough for the input data to
propagate to Q.
The set-up time can be NEGATIVE (if the transparency

window is longer than the delay from input to output).
This is attractive, as data can arrive at the register even after
the clock goes high, meaning that time can be borrowed from
the previous cycle.
Sequential Logic
63
B.Supmonchai
Sense Amp FF (StrongArm SA100)
Sense amplifier is a circuit that accept small swing input

signals and amplify them to full rail-to-rail signals
0 1
1
M2
1
M5
M9
M7
!S
Q
M1
M4
!R
M3
0
M6
1
M8
M10
0 1
clk
!Q
Sequential Logic
64
B.Supmonchai
Notes on Sensed Amp FF
The key is transistor M4 (in the middle of Sensed amp);

it delays signals that pass through to the other side of its
terminal, making the change on the other side slower
When D = 1, Y changes after X due to the delay of M4. By the
time M6 reacts to the change at its terminal, it is already

turned off by the terminal voltage at M4 (a 0). Thus, M6
holds a 1.
M4 also provides DC-leakage path to ground for either

node X or Y in case that the inputs change their value
after the positive edge of CLK arrives.
Advantages are reduced clock load and that it can be

used as a receiver for reduced swing differential buses
Where does the differential signal enter?
Sequential Logic
65
B.Supmonchai
Flipflop Comparison Chart

Name
Type
#clk ld
#tr
tset-up
thold
tpFF
Mux
Static
8 (clk-!clk)
20
3tpinv+tptx
tpinv+tptx
PowerPC
Static
8 (clk-!clk)
16
2-phase
Ps-Static
8 (clk1-clk2)
16
T-gate
Dynamic
4 (clk-!clk)
C2MOS
Dynamic
4 (clk-!clk)
TSPC
Dynamic
4 (clk)
11
S-O TSPC
Dynamic
2 (clk)
10
AMD K6
Dynamic
5 (clk)
19
SA 100
SenseAmp
3 (clk)
20
Sequential Logic
tptx
to1-1 2tpinv+tptx
tpinv
tpinv
3tpinv
66
B.Supmonchai
Choosing a Clocking Strategy
Choosing the right clocking scheme affects the

functionality, speed, and power of a circuit
Two-phase designs
+ robust and conceptually simple
- need to generate and route two clock signals
- have to design to accommodate possible skew between the
two clock signals
Single phase designs

+ only need to generate and route one clock signal
+ supported by most automated design methodologies
+ dont have to worry about skew between the two clocks
- have to have guaranteed slopes on the clock edges
Sequential Logic
67
B.Supmonchai
Non-Bistable Sequential Circuits
Previously, we have defined a circuit having two

stable states a bi-stable circuit
Other regenerative circuits, which are nonbistable:

Monostable
Only one stable state -> Pulse generators, One-shot circuits
Astable
No stable states -> Oscillator, On-chip clock generator
Schmitt Trigger
A special regenerative circuit exhibiting hysteresis in VTC.
Sequential Logic
68
B.Supmonchai
Schmitt Trigger
Non-Bistable Sequential Circuits
V OH
Vout
In
Out
2 important properties
V OL
Hysteresis
Fast Transition Time
at the output
VM
Sequential Logic
VM+
Vin
69
B.Supmonchai
Noise Suppression using Schmitt Trigger
VIN
VOUT
VM+
VM-
t0
t0 + t p
Example: Switch Debouncer

Sequential Logic
70
B.Supmonchai
CMOS Schmitt Trigger

VDD
M2
Moves switching
threshold of the
first inverter
M4
VIN
M1
VOUT
M3
Low-to-High
reff = kM1/(kM2 + kM4)
High-to-Low
reff = (kM1 + kM3)/kM2
Adapting the ratio between PMOS and NMOS, depending upon the
direction of the transition results in a shift in switching threshold
Sequential Logic
71
B.Supmonchai
Schmitt Trigger Simulated VTC

M1 = 1 m/0.25 m, M2 = 3 m/0.25 m, M3 = 0.5 m/0.25 m
M4 = k x 0.5 m/0.25 m
2.5
2.5
2.0
2.0
VM1
1.5
1.0
Vout(V)
Vout(V)
M4 = 1.5 m/0.25 m
VM2
1.5
1.0
k=1
k=3
0.5
0.0
0.0
k=2
0.5
0.5
1.0
1.5
Vin (V)
2.0
2.5
Voltage Transfer Characteristics

with hysteresis
0.0
0.0
k=4
0.5
1.0
1.5
Vin (V)
2.0
2.5
Effect of varying the ratio of the

PMOS device M4
Sequential Logic
72
B.Supmonchai
CMOS Schmitt Trigger (2)

How does the gate operate?
M4
M6
M3
VOUT
VIN
M2
M5
X
M1
Sketch VTC and find expression for VM- and VM+

Sequential Logic
73
B.Supmonchai
Review: Ring Oscillator

tp
3.0
2.5
V 1 V3 V 5
Period: T = 2 x tp x N
2.0
1.5
1.0
0.5
0.0
20.5
0.0
0.5
1.0
1.5
Different Clock Duty-Cycles

and phases can be derived
using simple logic operations
time (ns)
Sequential Logic
74
B.Supmonchai
Voltage Controller Oscillator (VCO)
Oscillation frequency of a VCO is a function (typically

nonlinear) of a control voltage
VDD
VDD
M6
M4
Schmitt Trigger
restores signal slopes
M2
In
M1
Ire f
Vcontr
Ire f
M3
M5
Current starved inverter
Delay of6a current starved inverter depends on the current

limit available to discharge the load capacitance of the gate
)
c
e
s
n
Sequential Logic
75
Vcontr
M3
M5
Current starv
B.Supmonchai
Current-Starved Inverter Simulation
tpHL (nsec)
6
)
c
e
s
n
(
t
L
H
p
4
2
0.0
0.5
1.5
V contr (V)
Vctrl (V)
2.5
Sequential Logic
The device is in the

subthreshold region
when Vctrl is smaller
than VT, resulting in
large variations of tp
as the drive current
is exponentially
dependent on the
propagat
drive voltage
of contro
Delay sensitive to
noise and variation

in Vctrl
76
B.Supmonchai
Differential Delay Element and VCO

- V o2
in 1
V o1 +
- in 2
v1
v2
v3
v4
V ctrl
two stage VCO
delay cell
- Inverting Inputs/Outputs
Oscillator with even number

+ Non-Inverting Inputs/Outputs of stages can be implemented
Differential-type VCO has better immunity to common mode

noise (e.g., supply noise) but consume more power
Sequential Logic
77
B.Supmonchai
2-Stage VCO Simulation

3.0
V1 V2
2.5
V4
2.0
1.5
1.0
0.5
0.0
2 0.5
0.5
1.5
2.5
3.5
time (ns)
The In-Phase and Quadrature Phase are produced simultaneously

Sequential Logic
78

Sequential Circuits: Boonchuay Supmonchai

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Sequential Circuits: Boonchuay Supmonchai

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Chapter 7

August 20, 2004; Revised - July 4, 2005

Goals of This Chapter

Implementation techniques for

Static versus Dynamic Realization

2102-545 Digital ICs

Static vs Dynamic Storage

connection between the output and the input

require periodic refresh

Latches versus Flipflops

Latches (with Clock)

high (or low) - transparent mode

when clock is low (or high) - hold mode

Review: The Regenerative Property

Small deviation from

If the gain in the

Review: Bistable Circuits

The cross-coupling of two

Have to be able to change the stored value by making A

2102-545 Digital ICs

Review: Clocked D Latch

Latches versus Flipflops II

stores data when

stores data when

2102-545 Digital ICs

Positive and Negative Latches

2102-545 Digital ICs

Setup time, tsetup is the time that the data inputs

Hold time, thold is the time that the data inputs

Propagation Delay, tc-q is the worst case

2102-545 Digital ICs

System Timing Constraints

tcd: contamination delay = minimum delay

tcdreg + tcdlogic thold

T tc-q + tplogic + tsu

Notes on System Timing Constraints

It is important to minimize the values of the timing

In modern high-performance systems, the register

the register overhead accounts for about 15% of the clock

Hold time becomes an issue when there is little logic

2102-545 Digital ICs

Building A (Static) Latch

Cutting the feedback loop

can implement as NMOS-only

MUX Based Latches

Change the stored value by cutting the feedback loop

Q = !clk & Q | clk & D

transparent when the

transparent when the

2102-545 Digital ICs

TG MUX Based Latch Implementation

Having to generate both clk and !clk

PT MUX Based Latch Implementation

Latch Race Problem

Which value of B is stored?

T tc-q + tplogic + tsu

Two-sided clock constraint

Master Slave Based ET Flipflop

2102-545 Digital ICs

* Ignore clk buffer

Assume propagation delays are tpd_inv and tpd_tx, that the

Set-up time - time before rising edge of clk that D must

Propagation delay - time for QM to reach Q