CENG3480_B2

Measurement Techniques
Reference: Chapter 3 Measurement Techniques of
High speed digital design , by Johnson and Graham

High-speed logic: Measurement

(v.9a)

Revision: frequency domain processing

and filtering

(1) Low-pass filter

(2) High-pass filter
(3) Band pass filter
(4) Tuned filter (narrow band pass filter)

See http://www.ee.duke.edu/~cec/final/node1.html

High-speed logic: Measurement (v.9a)

Revision: Filtering is in Frequency domain not

time domain
Filtering is in Frequency domain, dont mix up with high/low
amplitude levels
Higher amplitude
lower freq.

Lower amplitude
Higher freq.

amplitude

time
High-speed logic: Measurement (v.9a)

Examples of filters

0dB
gain
Freq.

R
0dB

Freq.

R
High-speed logic: Measurement (v.9a)

Analogies of Low-pass and High pass filters

High pass

Low pass

High-speed logic: Measurement (v.9a)

A common example of a low pass filter: An operational

amplifier:
Diagram of gain bandwidth product, from [1]

High-speed logic: Measurement (v.9a)

(1) Low pass filter (Frequency low than F-3dB can pass, or has
power gain more than 0.5)
(1) Low pass (e.g. op.amp)

At low freq, Gain=1=0dB

At -3dB cut off, gain = 0.5, = -3dB

E.g.
Ic(t)
R

C Vc

Vin

analog
system

Vout

Gain in dB = 20 log10(Vout/Vin)

3dB cut off point

-3dB
Frequency

B=Bandwidth
High-speed logic: Measurement (v.9a)

Flowpass(-3dB) =1/2RC
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(2) High pass filtering, (Frequency higher than F-3dB can pass, or
has power gain more than 0.5)
High pass

At low freq, Gain=0= -dB

At -3dB cut off, gain =0.5, = -3dB

Vin

analog
system

Vout

Gain in dB = 20 log10(Vout/Vin)

3dB cut off point

0
-3dB
Frequency

F-highpass(-3dB) = 1/2(L/R)
High-speed logic: Measurement (v.9a)

(3) Band - Pass Filters (Frequency within a range can pass)

E.g. A band-pass filter by combining a

low pass F low-pass(-3dB) filter ,
an ideal amplifier and
a high pass F high-pass(-3dB) filter.

R
Ideal amplifier

gain
0dB

3dB

Band width
High-speed logic: Measurement (v.9a)

(4) Tuned filter: special case of a band-pass filter -- only a

narrow band can pass
When the low pass F low-pass(-3dB), and the a high pass

F high-pass(-3dB)filter are close.

Fc=center frequency,

F=bandwidth (narrow)

R
C

gain
0dB
3dB

Fc =1/[2(LC)

1/2 ]

Frequency

Band width F
High-speed logic: Measurement (v.9a)

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Rise time and bandwidth of CRO probes

All scientific instruments have limitations
Limitations of oscilloscope systems

inadequate sensitivity
Usually no problem because except most sensitive digital network, we are
well above the minimum sensitivity (analogue system is more sensitive)

insufficient range of input voltage?

No problem. Usually within range

limited bandwidth?
some problems because all veridical amplifier and probe have a limited
bandwidth

Two probes having different bandwidth will show different

response.
Using faster probe
Using slower probe (6 MHz)

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Oscilloscope probes
Components of oscilloscope systems

Input signal
Probe
Vertical amplifier

We assume a razor thin rising edge. Both probe and vertical

amplifier degrade the rise time of the input signals.

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 Combined effects: approximation

Serial delay
The frequency response of a probe, being a combination of several random
filter poles near each other in frequency, is Gaussian.
1
2 2

Trise _ composite (T1 T2 TN )

2

Rise time is 10-90% rise time

When figuring a composite rise time, the squares of 10-90% rise times add

Manufacturer usually quotes 3-db bandwidth F3db

approximations T10-90= 0.338/F3dB for each stage (obtained by simulation)

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Example:
Given: Bandwidth of probe and scope = 300 MHz
Tr signal = 2.0ns
Tr scope = 0.338/300 MHz = 1.1 ns
Tr probe = 0.338/300 MHz = 1.1 ns
Tdisplayed = (1.12 + 1.12 +2.02)1/2
= 2.5 ns
For the same system, if Tdisplayed = 2.2 ns, what is the actual rise time?
Tactual = (2.22 - 1.12 1.12)1/2
= 1.6 ns

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Self-inductance of a probe ground loop

A Primary factor degrading the performance

Current into the probe must traverse the ground loop on the way back to source
The equivalent circuit of the probe is a RC circuit
The self-inductance of the ground loop, represented on our schematic by series
inductance L1, impedes these current.

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 Typically, 3 inches (of 0.02 Gauge wire loop) wire on

ground plane equals to (approx) 200 nH
Input C = 10pf
TLC = (LC)1/2 = 1.4ns
T10-90 = 3.4 TLC = 4.8ns
This will slow down the response a lot.
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Estimation of circuit Q
Output resistance of source combine with the loop inductance & input
capacitance is a ringing circuit.
Where
( L / C )1/ 2
Q
Rs

Q is the ratio of energy stored in the loop to energy lost per radian during
resonant decay.
Fast digital signals will exhibit overshoots. We need the right Rs to damp
the circuit. On the other hand, it slows down the response.

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 Impact: probe having ground wires, when using to view very fast signals
from low-impedance source, will display artificial ringing and overshoot.
A 3 ground wire used with a 10 pf probe induces a 2.8 ns 10-90% rise
time. In addition, the response will ring when driven from a lowimpedance source.

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Remedy
Try to minimize the earth loop wire

Grounding the probe close to the signal source

High-speed logic: Measurement (v.9a)

Back to page 29
19

Spurious signal pickup from probe ground loops

Mutual inductance between Signal
loop A and Loop B
LM 5.08

A1 A2
r3

where

A1 (A2) = areas of loops

r = separation of loops
Refer to figure for values.
In this example, LM = 0.17nH

Typically IC outputs

max dl/dt = 7.0 * 107 A/s

Vnoise LM

dI
(0.17nh)(7.0 107 V / s) 12mV
dt

12mV is not a lot until you have a 32-bit bus; must try to minimize loop area
High-speed logic: Measurement (v.9a)

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A Magnetic field detector

Make a magnetic field detector to test for noise

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How probes load down a circuit

Common experience

Circuit works when probe is inserted. It fails when probe is removed.

Effect is due to loading effect, impendence of the circuit has

changed. The frequency response of the circuit will change as
a result.
To minimize the effect, the probe should have no more than
10% effect on the circuit under test.

E.g. the probe impedance must be 10 times higher than the source
impedance of the circuit under test.

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An experiment showing the probe loading effect

A 10 pf probe loading a 25 ohm circuit

A 10 pf probe looks like 100 ohms to a 3 ns rising edge

Less probe capacitance means less circuit loading and better measurements.
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Special probing fixtures

Typical probes with 10 pf inputs and one 3 to 6 ground
wire are not good enough for anything with faster than 2ns
rising edges
Three possible techniques to attack this problem

Shop built 21:1 probe

Fixtures for a low-inductance ground loop
Embedded Fixtures for probing

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Shop-built 21:1 probe

Make from ordinary 50 ohm coaxial cable
Soldered to both the signal (source) and local ground
Terminates at the scope into a 50-ohm BNC connector

Total impedance = 1K + 50 ohms;

if the scope is set to 50 mv/divison,
the measured value is = 50 * (1050/50) = 1.05 V/division
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Advantages of the 21:1 probe

High input impedance = 1050 ohm
Shunt capacitance of a 0.25 W 1K resistor is around 0.5 pf,
that is small enough.

But when the frequency is really high, this shunt capacitance may
create extra loading to the signal source.

Very fast rise time, the signal source is equivalent to

connecting to a 1K load, the L/R rise time degradation is
much smaller than connecting the signal to a standard 10 pf
probe.

High-speed logic: Measurement (v.9a)

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Fixtures for a low-inductance ground loop

Refer to figure on page 19
Tektronix manufactures a probe fixture specially designed to
connect a probe tip to a circuit under test.

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Embedded Fixture for Probing

Removable probes disturb a
circuit under test. Why not
having a permanent probe
fixture?
The example is a very
similar to the 21:1 probe. It
has a very low parasitic
capacitance of the order 1
pf, much better than the 10
pf probe.

Use the jumper to select

external probe or internal
terminator.

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Avoiding pickup from probe shield currents

Shield is also part of a current path.

Voltage difference exists between logic ground and scope
chassis; current will flow.
This shield current * shield resistance R shield will produce
noise Vshield
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 VShield is proportional to shield resistance, not to shield

inductance because the shield and the centre conductor are
magnetically coupled. Inductive voltage appear on both
signal and shield wires.
To observe VShield

Connect your scope tip and ground together

Move the probe near a working circuit without touching anything. At
this point you see only the magnetic pickup from your probe sense
loop
Cover the end of the probe with Al foil, shorting the tip directly to the
probes metallic ground shield. This reduces the magnetic pickup to
near zero.
Now touch the shorted probe to the logic ground. You should see only
the VShield
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Solving VShield problem

Lower shield resistance (not possible with standard probes)
Add a shunt impedance between the scope and logic ground.

Not always possible because of difficulties in finding a good

grounding point

Turn off unused part during observation to reduce voltage

difference

Not easy

Use a big inductance (magnetic core) in series with the shield

Good for high frequency noise.

But your inductor may deteriorate at very high frequency.

Redesign board to reduced radiated field.

Use more layers

Disconnect the scope safety ground

Not safe
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 Use a 1:1 probe to avoid the 10 time magnification when

using 10X probe
Use a differential probe arrangement

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Viewing a serial data transmission system

Jitter observed due to intersymbol interference and additive
noise.
To study signal, probe point D and use this as trigger as well.

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 No jitter at trigger point due to repeated syn with positivegoing edge.

This could be misleading

For proper measurement, trigger with the source clock

The jitter is around half of the previous one.

If source clock is not available, trigger on the source data signal point
A or B (where is minimal jitter)

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Slowing Down the System clock

Not easy to observe high speed digital signals which include
ringing, crosstalk and other noises.
Trigger on a slower clock (divide the system clock) allows
better observations because it allows all signals to decay
before starting the next cycle.
It will help debugging timing problems.

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Observing crosstalk
Crosstalk will

Reduce logic margins due to ringing

Affect marginal compliance with setup and hold requirements
Reduce the number of lines that can be packed together

Use a 21:1 probe to check crosstalk

Connect probe and turn off machine; measure and make sure there is
minimal environment noise.
Select external trigger using the suspected noise source
Then turn on machine to observe the signal which is a combination of
primary signal, ringing due to primary signal, crosstalk and the noise
present in our measurement system

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 Try one of the followings to observe the cross talk

Turn off primary signal (or short the bus drivers)

Varying the possible noise source signal (e.g. signal patterns for the bus)

Compare signals when noise source is on and off

Talk photos with the suspected noise source ON and source OFF.
The difference is the crosstalk

Generating artificial crosstalk

Turn off, disabled, short the driving end of the primary signal. Induce a
step edge of know rise time on the interfering trace and measure the
induced voltage.
Useful technique when measuring empty board without components.

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Measuring Operating Margins

In digital system measurements, we are interested to stress the system to
ensure the system is within operation margin specified.
Make sure the arrangement is automatic and self recovery
Some of the common tests

Additive noise

Add random noise to every node

Sine waves, square waves or random pattern
Difficult to administer
Suitable for data receivers and transmitters

Adjusting the timing of a large bus (clock skew margin test)

Test the combine effects of system setup time, hold time and operating margin etc.
Connect the devices clock signals using the following methods.
Clock adjustment by coax delay (vary the length)
Clock adjustment by pulse generator (variable delays)
Simple circuits for clock phase adjustment
Clock adjustment by a phase-locked loop
Clock adjustment by voltage variation
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Power Supply
Power supply variation can change response characteristics
Vary the supply over a + 10% range

Temperature
Temperature will vary the delay characteristics
Can use cooling spray, blow dryer etc. Some companies use temperature
control ovens
Make sure the temperature probe is attached to the right place

Data Throughput
Compose a suite of operations that exercise each individual connections
Not easy to compose test pattern that represents the real situations. Often
system passes tests but fails at real operations.
Good data pattern will uncover unexpected avenues of noise coupling
which causes failures
Complex tests are expensive

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