ARM

Why ARM here?

ARM is one of the most licensed and thus
widespread processor cores in the world
Used especially in portable devices due to low
power consumption and reasonable
performance (MIPS / watt)
Several interesting extensions available or in
development like Thumb instruction set and
Jazelle Java machine

INTRODUCTION
ARM is a RISC processor.
It is used for small size and high performance
applications.
Simple architecture low power consumption.

BRIEF HISTORY OF ARM

1985: Acorn Computer Group manufactures the
first commercial RISC microprocessor.
1990: Acorn and Apple participation leads to the
founding of Advanced RISC Machines (A.R.M.).
1991: ARM6, First embeddable RISC
microprocessor.
1992 1994: Various companies use ARM
(Sharp, Samsung), while in 1993 ARM7, the first
multimedia microprocessor is introduced.

CONT
1995: Introduction of Thumb and ARM8.
1996 2000: Alcatel, Huindai, Philips, Sony, use
RM, while in 1999 ARM cooperates with
Erickson for the development of Bluetooth.
2000 2002: ARMs share of the 32 bit embedded
RISC microprocessor market is 80%. ARM
Developer Suite is introduced.

ARM ARCHITECTURE
Simple architecture
+
Simple instruction set
+
Code density

Small size

Low power
consumption

Cont..
32-bit RISC-processor core (32-bit instructions)
32-bit integer registers (16 available)
Von Neuman-type bus structure (ARM7), Harvard
(ARM9)
8 / 16 / 32 -bit data types
7 modes of operation (usr, fiq, irq, svc, abt, sys, und)
Simple structure -> reasonably good speed / power
consumption ratio

ARM core modes of operation:

User (usr): Normal program execution state
FIQ (fiq): Data transfer state (fast irq, DMA-type transfer)
IRQ (iqr): Used for general interrupt services
Supervisor (svc): Protected mode for operating system
support
Abort mode (abt): Selected when data or instruction fetch is
aborted
System (sys): Operating system privilege-mode for user
Undefined (und): Selected when undefined instruction is
fetched

ARM register set

Register structure depends on mode of operation
16 pieces of 32-bit integer registers R0 - R15 are
available in ARM-mode (usr, user)
R0 - R12 are general purpose registers
R13 is Stack Pointer (SP)
R14 is subroutine Link Register
R15 is Program Counter (PC)
R16 is state register (CPSR,Current Program Status
Register)

Cont..
There are 37 ARM registers in total of which variable amount
is available as banked registers depending on the mode of
operation
R13 functions always as stack pointer and R14 functions as
link register in other than sys and usr modes
SPSR = Saved Program Status Register
Flag register Mode-bits tell the processor operating mode and
thus the registers available

Program Status Registers

31

28 27

24

NZ C V Q
f

16 15

U n d e f i n e d
s
x

Condition code flags

23

N = Negative result from ALU

Z = Zero result from ALU
C = ALU operation Carried out
V = ALU operation oVerflowed

J = 1: Processor in Jazelle state

I F T mode
c

Interrupt Disable bits.

T Bit
Architecture xT only
T = 0: Processor in ARM state
T = 1: Processor in Thumb state

Sticky Overflow flag - Q flag

J bit

I = 1: Disables the IRQ.

F = 1: Disables the FIQ.

Indicates if saturation has occurred

Mode bits
Specify the processor mode

When the processor is executing in ARM state:

All instructions are 32 bits wide
When the processor is executing in Thumb state:
All instructions are 16 bits wide
When the processor is executing in Jazelle state:
All instructions are 8 bits wide
Processor performs a word access to read 4
instructions at once

Memory Organization
bi t 3 1

bi t 0

23

22

21

20

19

18

17

16

Address bus: 32 bits

1 word = 32 bits

w ord16
15

14

13

12

half -w ord14 half -w ord12

11

10

w ord8
7

by te6 half -w ord4

3

by te
address

by te3 by te2 by te1 by te0

ARM

System - On - Chip Architecture

15

Load-Store Architecture
ARM employs as load-store architecture.
The instruction set will only Process the values which
are in resisters(specified directly within the
instruction itself).
The only operations which apply to memory state are
ones which copy memory values to register(load
instruction).
Copy register values to memory (store instruction).
ARM does not support the memory-memory
operations

Instruction Set
Three instruction types
Data processing
Data transfer
Control flow

17

I/O System
ARM handles peripherals as memory mapped devices
with interrupt support.
Interrupts:
IRQ: normal interrupt
FIQ: fast interrupt

18

ARM ORGANIZATION AND

IMPLEMENTATION
ARM has two styles of processor core

- 3-stage pipeline ARM organization

- 5-stage pipeline ARM organization

3-Stage Pipeline (ARM0 ARM7)

Fetch
Decode
Execute

Throughput:
1 instruction / cycle

A[31:0]

control

address r egister
P
C

incr ementer

PC
r egister
bank
instr uction
decode
A
L
U
b
u
s

multiply
r egister

&

b
u
s

b
u
s

barr el
shif ter

control

ALU

data out r egister

data in r egister
D[31:0]

5 stage pipeline
Program execution time:

T prog

N inst CPI

f clk

Ways to reduceT prog :

Increase

f clk

Logic simplification

Reduce CPI
multicycle instruction.
ARM

reduce the number of

System - On - Chip Architecture

22

5 stage pipeline (ARM9)

Fetch
Decode
Execute
Buffer / Data
Write - Back

ARM Instruction Execution

Data Processing Instructions:
Only one instruction execute per clock cycle.
Register-Register operations
Register-Immediate operations
Data Transfer Instructions:
It has two clock cycle.
First cycle-compute address
Second cycle-transfer the data
Branch instruction:
First cycle-compute branch target
Second cycle-save return address

ARM instruction set

Fully 32-bit instruction set in native operating mode
32-bit long instruction word
All instructions are conditional
Normal execution with condition AL (always)
For a RISC-processor, the instruction set is quite
diverse with different addressing modes
36 instruction formats

ARM instruction set

All instructions are conditional
In normal instruction execution (unconditional)
condition field contents of AL is used (Always)
In conditional operations one of the 14 available
conditions is selected

Branching
BX, Branch and eXchange

Branch with instruction set exchange (ARM <-> Thumb)

B and BL

Branch with 24-bit signed offset

Link: PC -> R14

Data processing
AND, EOR, SUB, RSB, ADD,ADC, SBC, RSC, TST, TEQ,CMP,
CMN, ORR, MOV, BIC,MVN
Multiple operation instruction
Arithmetic Operations
ADD r0, r1, r2 ; r0:= r1+r2 and dont update flags
ADDS r0, r1, r2 ; r0:= r1+r2 and update flags
Logical Operations
AND r0, r1, r2 ; r0:= r1 AND r2
Register Movement
MOV r0, r2
Comparison
CMP r1, r2

MULTIPLICATION
MUL,MLA

MULL,MLAL

DATA TRANSFER
LDR,STR

Exception
SWI: Software Interrupt
Transfers execution to address in memory location 0x8 and
changes the mode to svc.
Comment field allows the interrupt service to determine the
wanted action for SWI.

Other instructions
Coprocessor instructions: CDP, LDC, STC,MRC, MCR
ARM does not execute these instructions but lets a coprocessor
to handle them
CDP:

Undefined instruction:

THUMB INSTRUCTION
T (Thumb)-extension shrinks the ARM instruction set to 16-bit
word length -> 35-40% saving in amount of memory compared to
32-bit instruction set.

Thumb-state registers
Only lower part of the register immediately available
Upper register set (R8-R15) can be used with assembler code

Format 1 and Format 2

Format 1: Move shifted register
LSL, LSR, ASR
ex. LSL Rd, Rs, #offset shifts Rs left by #offset and stores the
result in Rd

Format 2: Add/subtract
ADD, SUB
ex. ADD Rd, Rs, Rn; adds contents of Rn to contents of Rs and
places the result in Rd

Format 3:
Move/compare/add/subtract immediate
MOV, CMP, ADD, SUB
ex. MOV R0, #128

Format 4:
ALU operations
16 different arithmetic /logical operations for registers, see
table
ex.MUL R0, R7 ;R0 = R7*R0

Format 5:
Hi register operations /branch exchange

Format 6:
PC relative load
ex. LDR Rd, [PC, #imm] adds unsigned offset (255
words,1020 bytes) in imm to the current value of the PC.

Format 7:
Load/store with register offset LDR, LDRB, STR, STRB
ex. STR Rd,[Rb, Ro] calculates the target
address by adding together Rb and Ro and stores the contents of
Rd at the address

Format 8:
Load / store signextended byte / halfword
LDSB, LDSH, LDRH, STRH

Format 9:
Load / store with immediate offset
LDR, LDRB, STR, STRB

Format 10:
Load / store halfword
LDRH, STRH

Format 11:
SP-relative load /store
LDR, STR

Format 12:
Load address

Format 13:
Add

offset to Stack Pointer

Format 14:
Push / pop registers
PUSH, POP

Format 15:
Multiple

load / store
LDMIA, STMIA

Format 16:
Conditional branch
BEQ, BNE, BCS, BCC, BMI,BPL, BVS, BHI, BLS, BGE,BLT,
BGT, BLE.

Format 17:
Software interrupt
SWI value8
Used to enter interrupt routine (svc mode) pointed by contents of
address 0x8.Interrupt service is executed in ARM-state.

Format 18:
Unconditional

branch
B label, ARM equivalent BAL

Format 19:
long branch with link
BL label
32-bit instructions in two half words: Instruction 1 (H=0) contains
the upper 11 bits of the target address. Instruction 2 (H=1) contains
the lower 11 bits of the target address.