Design and Verification of USB 3.

0
Physical Layer
G u i d e d B y : P r o f. M a d h u s h a n k a r a M .
P r o f. S u n d a r e s a n C . ( S e l e c t i o n G r a d e )
SOIS, Manipal University
Manipal

B y : H a r d i k Tr i v e d i ( 1 2 1 0 2 4 0 4 8 )

AGENDA

Introduction

USB 3.0 Super Speed Physical Layer

PHY Design
PHY Transmitter
PHY Receiver

PHY Verification using SV

SV Testbench Environment

Simulation Results & Coverage Report

Conclusion

References
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DESIGN AND VERIFICATION OF USB 3.0 PHYSICAL LAYER

Introduction
Universal Serial Bus (USB) is specification developed by Compaq, Intel,
Microsoft and NEC.
Main goal of USB protocol was to replace the no. of different ports of PC
Connectivity.
USB is by far most widely used PC interface now a days.
Version 1.0 was 1st presented in 1996 and also known as FULL Speed USB.
Version 2.0 was released in 2001 was termed as HI Speed USB.
In 2008 the faster version of USB was released i.e. USB 3.0 known as Super
Speed USB.

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DESIGN AND VERIFICATION OF USB 3.0 PHYSICAL LAYER

USB 3.0 Super Speed Physical

Layer
Super Speed PHY Layer handles the low level USB Super Speed protocol
and signaling.
It includes following features,
Standard PHY interface enables multiple IP Sources.
Supports 5.0GT/s serial data transmission rate.
Utilize 8bits, 16bits or 32bits parallel interface to transmit and receive
Allow integration of high speed components into single functional block as seen
by the endpoint device manager.
Data and clock recovery from serial stream.
Holding registers to transmit and receive data.
Support direct disparity control for transmitting compliance patterns.
8b/10b encode/decode and error indication.
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PHY Transmitter

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DESIGN AND VERIFICATION OF USB 3.0 PHYSICAL LAYER

Scrambler (Optional
8b/16b/32b)
Scrambler eliminates generation of repetitive patterns on a transmitted
data stream.
Repetitive patterns results in large amount of energy concentrated in
discrete frequencies.
Eg. Repetitive patterns such as 10101010 are eliminated.

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8b/10b Encoder

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Parallel to Serial Converter

The Parallel-to-Serial converter clocks 10-bit symbols out in the bit order
'abcdeifghj', with the least significant bit (a) shifted out first and the most
significant bit (j) shifted out last.
The symbols supplied by the 8b/10b Encoder are clocked into the converter
at 250MHz.
The serial bit stream is clocked out of the Parallel-to-Serial converter at
2.5GHz.

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DESIGN AND VERIFICATION OF USB 3.0 PHYSICAL LAYER

PHY Receiver

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Clock and Data Recovery

Using a PLL (Phase-Locked Loop),
the receiver circuit generates the
Rx Clock from the data bit
transitions in the input data
stream.
The Rx Clock is used to clock the
inbound serial symbol stream into
the Serial-to-Parallel converter
(Deserializer).
The Rx Clock is different from the
Local Clock that is used to clock
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DESIGN
AND VERIFICATION OF USB 3.0 PHYSICAL LAYER
symbols out of the Elastic
Buffer

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Serial to Parallel Converter

The incoming serial data on each Lane is clocked into the serial-to-parallel
converter by the Rx - clock.
The 10-bit symbols produced are clocked into an Elastic Buffer using a
divide-by-10 version of the Rx Clock.

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Elastic Buffers Role

To compensate for the frequency difference between the Rx Clock and local
Clock an elastic buffer is incorporated in the very early stage of the receive
path.
The Elastic Buffer compensates for the difference between the two clocks
by either deleting or inserting SKP symbol.
Deleting or adding a SKP symbol in the Elastic Buffer prevents a buffer
overflow or underflow conditions.

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8b/10b Decoder

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PHY Verification

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What is Verification ?
Process of demonstrating
functional correctness of a
design.
Process that ensures specification
is preserved in the
implementation.

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The Need For Verification

Verification is different from design but it requires complete knowledge of
the design.
A primary purpose of verification is about finding failures, identifying bugs
and correcting before they are mapped into the IC.
70 % of design effort goes to verification.

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SV Testbench Environment
Environment

Test

Stimulus
Generator

Driver

Scoreboard

Coverage

Monitor

DUT

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Stimulus Generator
It generates stimulus which are sent to DUT by driver.
It should be able to generate every possible scenario.
User should be able to control the generation from directed and directed
random test cases.

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Driver
A typical driver repeatedly receives a data items and drives it to DUT by
sampling and driving the DUT signals.
The drivers duty is to drive data items to the bus according to the
interface protocol.
The driver translate the operations produced by the generator into the
actual inputs for the design under verification according to the design
specifications.

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Monitor (Receiver)
Monitor reports the protocol violation and identifies all the transactions.
The monitor is responsible for collecting data from the bus and converting
it into events and information.

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Scoreboard
Scoreboard stores the expected DUT output.
Checker :
Checker is a part of scoreboard.
Checker must validate that the actual results match the expected
ones.

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Environment
Environment contains the instances of the entire verification component
and Component connectivity.
Construct objects like driver, monitor and scoreboard.
Reset the DUT to set all signal to a known state.
Start Verification by call methods declared in objects.

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Tests
Tests is a program block which should be able to control the Testbench
features.
It can communicate all Testbench components.

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Simulation Results (Design)

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Simulation Results (Verification)

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Functional Coverage Report

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Scoreboard Console Results

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Conclusion
Through this project I understand the concept of USB 3.0 and Serial data communication.
In this project I am able to transfer data on 2.5GHz clock.
I also understand 8b/10b encoder and decoder and how they provide a dc balanced data.
I understands the concept of verification using System Verilog.
I wrote an exhaustive verification plan according to the specifications and I created
verification environment and wrote test cases to verify design in System Verilog.

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References
[1] Universal Serial Bus 3.0 Specification, Revision 1.0, November 12, 2008.
[2] Data Manual Texas Instruments, Literature number: SLLSE16E, June 3,
2011
[3] A.X. Widmer and P.A. Franaszek, A dc-balanced, artitioned block, 8B/10B
transmission
code, IBM ournal of Research and Development, vol.27,
no.5, pp.440- 451, Sep 1983.
[4] Universal Serial Bus 2.0 Specification, Revision 1.0, March 13, 2006.
[5] PHY interface for the PCI Express and USB 3.0 Architecture, March 11,
2009.
[6] Lattice Semiconductor Corporation 8b/10b Encoder/Decoder, February
2012.
[7] Ching-Che Chung, Chen-Yi Lee, An All-Digital Phase Locked Loop for high
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speed
clock generation, February
6, 2003.

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References (Continues)
[8] Clifford E. Cummings and Peter Alfke, Simulation and Synthesis
Techniques for Asynchronous FIFO Design with Asynchronous Pointer
Comparisons, SNUG 2002.
[9] Ravi Budruk, Don Anderson & Tom Sanely, 2004. PCI Express System
Architecture, Mindshare Inc., pp 419-434.
[10] Thatcher, Jonathan (1996-04-01). Thoughts on Gigabit Ethernet
Physical, IBM Retrieved on 2008-08-17.
[11] Jenming Wu & Yu-Ho Hsu, 8B/10B Codec for Efficient PAPR Reduction in
OFDM Communication Systems, International technology roadmap for
Semiconductors (ITRS).
[12] Test Bench Architecture in System Verilog, WWW.TESTBENCH.IN

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Thank You
ANY QUERIES ???

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