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Domino Logic

Based 2 Bit
Comparator

ABSTRACT
Comparison is most basic arithmetic operation that
determines if one number is greater than, equal to, or less
than the other number.
Comparators

are widely used in circuits, such as highperformance microprocessors, communication systems,


and many other systems.
Even though comparator logic design is straightforward
the extensive use of comparators in high-performance
systems places a great importance on performance and
power consumption optimizations . A faster and power
efficient comparator is thus desirable.

WHAT IS A COMPARATOR?
Magnitude comparator is a
combinational circuit that compares
two numbers, A and B, and
determines their relative
magnitudes.

The circuit, for comparing two n-Bit


numbers, has 2n inputs & 2^2n entries in
the truth table

Truth Table
INPUT

A1
0
0

0
0

0
0

0
0

0
0

1
1

0
0

0
0

0
1

1
1

1
0

0
1

0
0

0
0

0
1
0

1
0

1
0
0

0
0

1
1

1
1

OUTPUT

A>B A=B A<B


0
1
0
0
0
1

B0
0
1

B1
0
0

0
0

A0
0
0

Logic Diagram for 2 bit


comparator

Digital
Circuits

Static Circuits

Classical
CMOS

Transmissio
n Gates

Dynamic Circuits

Pseudo
NMOS

Pass
Transisto
r

Domino Logic

Design
produces
Large
Power
dissipation in comparison to remaining
three logic styles.
Design requires large number of
transistors because for every input both
(NMOS & PMOS) are used
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10

Design requires
transistors

large

number

of

It produces Large Power dissipation


than PTL and Pseudo logic styles.
Design is much complex because
Control signal requires both true &
complimentary form.
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12

It does not provide full output voltage swing


because PMOS is always ON by which output
resistance is increased then always degraded
output is obtained.
Low noise margin due to high VOL.
It
produces
non-zero
static
power
dissipation due to always ON PMOS load
device. When NMOS network is turned ON, a
direct path between supply voltage and
ground exists and then conducts steady
state current.

13

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It does not provide full output


voltage swing because PMOS is not
used.
Design
produces
threshold
loss
because it uses only NMOS transistors
to pass both Low & High (0 & 1)
inputs.

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PARAMETER

CONVENTIONAL

DYNAMIC

Transistor used

2N

N+4

Speed

less

more

Area used

more

less

Power dissipation

more

less

Delay

more

less

Noise margin

low

high

Efficiently

less

more

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EQUATIONS FOR TWO BIT


COMPARATOR
USING KARNAUGH MAPS EQUATIONS FOR
A>B , A=B and A<B are :For A>B - A1B1+ AoBo(A1B1+A1B1)
For A=B - (A1B1+A1B1)(AoBo+AoBo)
For A<B A1B1+AoBo(A1B1+A1B1)

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DOMINO CIRCUIT FOR


A>B

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DOMINO CIRCUIT FOR


A=B

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DOMINO CIRCUIT FOR

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Dynamic CMOS Logic


Here, the output of the first dynamic CMOS stage
drives one of the inputs of the second dynamic CMOS stage .

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During the precharge phase, both output voltages Vout1 and


Vout2 are pulled up by the respective pMOS precharge devices.
Also, the external inputs are applied during this phase. The input
variables of the first stage are assumed to be such that the
output Vout1 will drop to logic "0" during the evaluation phase.
On the other hand, the external input of the second-stage NAND2
gate is assumed to be a logic " 1,.
When the evaluation phase begins, both output voltages are
logic-high.
The output of the first stage eventually drops to its correct logic
level after a certain time delay. However, since the evaluation in
the second stage is done concurrently, starting with the high
value of Vout1 at the beginning of the evaluation phase, the
output voltage Vout2 at the end of the evaluation phase will be
erroneously low. Although the first stage output subsequently
assumes its correct output value once the stored charge is
drained, the correction of the second-stage output is not
possible.

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CMOS Domino Logic

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During the precharge phase (when CK = 0), the output node of the dynamic CMOS
stage is precharged to a high logic level, and the output of the CMOS inverter becomes
low. When the clock signal rises at the beginning of the evaluation phase, there are two
possibilities: The output node of the dynamic CMOS stage is either discharged to a low
level through the nMOS circuitry (1 to 0 transition), or it remains high.
Consequently, the inverter output voltage can also make at most one transition during
the evaluation phase, from 0 to 1. Regardless of the input voltages applied to the
dynamic CMOS stage, it is not possible for the buffer output to make a 1 to 0 transition
during the evaluation phase.
The problem in cascading conventional dynamic CMOS stages occurs when one or
more inputs of a stage make a 1 to 0 transition during the evaluation phase .On the
other hand, if we build a system by cascading domino CMOS logic gates ,all input
transistors in subsequent logic blocks will be turned off during the precharge phase,
since all buffer outputs are equal to 0. During the evaluation phase, each buffer output
can make at most one transition (from 0 to 1), and thus each input of all subsequent
logic stages can also make at most one (0 to 1) transition.
In a cascade structure consisting of several such stages, the evaluation of each stage
ripples the next stage evaluation, similar to a chain of dominos falling one after the other.
The structure is hence called domino CMOS logic.

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NMOS Circuit of Domino logic based 2 bit comparator

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NEED OF DOMINO LOGIC

Domino logic is a CMOS based evaluation of the


dynamic logic techniques which are based on the
either PMOS or NMOS transistors.
It was developed to speed up the circuits. The
dynamic gate outputs connect to one inverter, in
domino logic.

Domino runs 1.5-2 times faster than static CMOS


logic because dynamic gates present much lower
input capacitance for the same output current and a
lower switching threshold.

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Advantages
Speed advantages

Reduced fighting during transitions


Fewer transistors per gate, lower capacitive load
Area advantages
Mainly consists of NMOS
N+4 transistors instead of 2N transistor per gate

Disadvantages
Non-inverting nature may require logic duplication
Strict timing constraints
Charge sharing, noise susceptibility
High clock routing overhead

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CONCLUSION
Less number of transistors are used in

Domino logic as compared to conventional


CMOS logic.

Because of less transistors, the delay will be

less, and because of the less delay speed of


the domino CMOS logic will be high.
Because of less transistors used there will be

less power dissipation as compared to that


of conventional CMOS logic.

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References
Circuits, Power and Computing Technologies (ICCPCT), 2013

International Conference on/ 20-21 March 2013/ Nagercoil,India

CMOS VLSI Design - Neil H. E. Weste,David Harris, Ayan Banerjee.


CMOS Digital IC Design-Yusuf Leblibici & Kang.
Folegnani, D. and Gonzalez, A., EnergyEffective Issue Logic, in Proc.

ISCA, 2001, pp. 230239.

Digital Integerated Circuits Jan M. Rabaey.


Anjuli, Satyajit Anand , 2-Bit Comparator Using Different Logic Styles,

International Journal of Engineering Science Invention, January 2013.

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Thanks
For Your
Patient
Listening

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