Beruflich Dokumente
Kultur Dokumente
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3-<1>
Chapter 3 :: Topics
Introduction
Latches and Flip-Flops
Synchronous Logic Design
Finite State Machines
Timing of Sequential Logic
Parallelism
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3-<2>
Introduction
Outputs of sequential logic depend on current and
prior input values it has memory.
Some definitions:
State: all the information about a circuit necessary to
explain its future behavior
Latches and flip-flops: state elements that store one bit
of state
Synchronous sequential circuits: combinational logic
followed by a bank of flip-flops
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Sequential Circuits
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State Elements
Bistable circuit
SR Latch
D Latch
D Flip-flop
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Bistable Circuit
Fundamental building block of other state elements
Two outputs: Q, Q
No inputs
I2
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I1
I1
I2
3-<6>
1
0
I1
I2
I1
I2
SR (Set/Reset) Latch
SR Latch
N1
N2
S = 1, R = 0
S = 0, R = 1
S = 0, R = 0
S = 1, R = 1
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SR Latch Analysis
S = 1, R = 0: then Q = 1 and Q = 0
S = 0, R = 1: then Q = 0 and Q = 1
R
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N1
N2
N1
N2
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SR Latch Analysis
S = 1, R = 0: then Q = 1 and Q = 0
0
N1
S = 0, R = 1: then Q = 0 and Q = 1
R
0
1
N2
1
N1
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0
0
N2
3-<10>
SR Latch Analysis
S = 0, R = 0: then Q = Qprev
Qprev = 0
R
N1
Qprev = 1
N2
N1
N2
S = 1, R = 1: then Q = 0 and Q = 0
R
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N1
N2
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SR Latch Analysis
S = 0, R = 0: then Q = Qprev and Q = Qprev (memory!)
Qprev = 0
R
Qprev = 1
0
N1
0
0
N1
0
1
N2
1
0
N2
1
N1
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0
1
N2
3-<12>
SR Latch Symbol
SR stands for Set/Reset Latch
Stores one bit of state (Q)
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SR Latch
Symbol
R
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D Latch
Two inputs: CLK, D
CLK: controls when the output changes
D (the data input): controls what the output changes to
Function
When CLK = 1, D passes through to Q (the latch is transparent)
When CLK = 0, Q holds its previous value (the latch is opaque)
D Latch
Symbol
CLK
D
Q
Q
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3-<14>
CLK D
0
X
1
0
1
1
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R
S
CLK
Q Q
Q Q
Q
Q
3-<15>
CLK D
0
X
1
0
1
1
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D
X
1
0
R
S
Q Q
Q Q
S
0
0
1
R
0
1
0
CLK
D
Q
Q
Q
Q
Qprev Qprev
0
1
1
0
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D Flip-Flop
Two inputs: CLK, D
Function
The flip-flop samples D on the rising edge of CLK
When CLK rises from 0 to 1, D passes through to Q
Otherwise, Q holds its previous value
Q
Q
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When CLK = 1
L2 is transparent
L1 is opaque
N1 passes through to Q
CLK
CLK
D D
L1
Q
Q
N1
CLK
D
Q Q
L2
Q Q
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Q
Q
Q
Q
CLK
D
Q (latch)
Q (flop)
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Q
Q
Q
Q
CLK
D
Q (latch)
Q (flop)
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Registers
CLK
D0
D1
Q0
CLK
Q1
D3:0
D2
Q2
D3
Q3
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Q3:0
3-<21>
Enabled Flip-Flops
Inputs: CLK, D, EN
The enable input (EN) controls when new data (D) is stored
Function
EN = 1
D passes through to Q on the clock edge
EN = 0
Internal
Circuit
EN
0
D
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Symbol
CLK
Q
EN
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Resettable Flip-Flops
Inputs: CLK, D, Reset
Function:
Reset = 1
Q is forced to 0
Reset = 0
the flip-flop behaves like an ordinary D flip-flop
Symbols
Reset
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Resettable Flip-Flops
Two types:
Synchronous: resets at the clock edge only
Asynchronous: resets immediately when Reset = 1
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Resettable Flip-Flops
Two types:
Synchronous: resets at the clock edge only
Asynchronous: resets immediately when Reset = 1
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Settable Flip-Flops
Inputs: CLK, D, Set
Funtion:
Set = 1
Q is set to 1
Set = 0
the flip-flop behaves like an ordinary D flip-flop
Symbols
Set
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Sequential Logic
Sequential circuits: all circuits that arent combinational
A problematic circuit:
X
X
Y
Z
0 1 2 3 4 5 6 7 8 time (ns)
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3-<27>
Sequential Logic
Sequential circuits: all circuits that arent combinational
A problematic circuit:
X
Y
Z
0 1 2 3 4 5 6 7 8 time (ns)
3-<28>
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3-<29>
CLK
S
Next
State
S
Current
State
Next State
Logic
CL
Next
State
Output
Logic
CL
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Outputs
3-<30>
inputs
next
state
logic
CLK
next
k state
k
state
output
logic
outputs
Mealy FSM
inputs
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next
state
logic
CLK
next
k state
k state
output
logic
outputs
3-<31>
Bravado
LA
Academic
Labs
TB
TA
LA
TA
TB
Blvd.
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LB
LB
Ave.
Dorms
Fields
3-<32>
TA
TB
Traffic
Light
Controller
LA
LB
Reset
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S1
LA: yellow
LB: red
S3
LA: red
LB: yellow
S2
LA: red
LB: green
TB
TB
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Next
State
Inputs
TA
TB
S0
S0
S1
S2
S2
S3
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S'
3-<36>
Next
State
Inputs
TA
TB
S'
S0
S1
S0
S0
S1
S2
S2
S3
S2
S2
S3
S0
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3-<37>
Inputs
Next State
S1
S0
TA
TB
S'1
S'0
State
Encoding
S0
00
S1
01
S2
10
S3
11
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3-<38>
Inputs
Next State
S1
S0
TA
TB
S'1
S'0
State
Encoding
S0
00
S1
01
S2
10
S3
11
S'1 = S1 S0
S'0 = S1S0TA + S1S0TB
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Outputs
LA1
S0
green
00
yellow
01
red
10
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LA0
LB1
LB0
Output Encoding
S1
3-<40>
Outputs
Output Encoding
S1
S0
LA1
LA0
LB1
LB0
green
00
yellow
01
red
10
LA1 = S1
LA0 = S1S0
LB1 = S1
LB0 = S1S0
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S1
S'0
S0
r
Reset
state register
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TA
S'1
S1
S'0
S0
r
TB
Reset
S1
inputs
S0
next state logic
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state register
3-<43>
LA1
S1
LA0
TA
S'0
S0
LB1
r
TB
Reset
S1
inputs
S0
LB0
next state logic
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state register
output logic
3-<44>
outputs
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
Cycle 8
Cycle 9
Cycle 10
CLK
Reset
TA
TB
S'1:0
??
S1:0
??
S0 (00)
S1
LA1:0
??
Green (00)
Yellow (01)
LB1:0
??
Red (10)
S0 (00)
S1 (01)
S2
S3
(10)
(01)
(11)
S2 (10)
S3 (11)
Red (10)
15
20
25
30
S1
S0 (00)
35
40
45
TA
Reset
S0
LA: green
LB: red
S3
LA: red
LB: yellow
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TA
S1
LA: yellow
LB: red
S2
LA: red
LB: green
TB
TB
(01)
Green (00)
Green (00)
10
S0 (00)
3-<45>
t (sec)
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3-<46>
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3-<47>
S0
0
S1
0
S2
0
S3
0
S4
1
0
Mealy FSM
reset
1/1
1/0
S0
1/0
S1
0/0
0/0
S2
1/0
S3
0/0
0/0
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3-<48>
S1
S0
State
Encoding
S0
000
S1
001
S2
010
S3
011
S4
100
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S'2
S'1
S'0
3-<49>
S1
S0
S'2
S'1
S'0
State
Encoding
S0
000
S1
001
S2
010
S3
011
S4
100
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Current State
Output
S2
S1
S0
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Current State
Output
S2
S1
S0
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Y = S2
3-<52>
Current State
Input
Next State
S1
S0
State
Encoding
S0
00
S1
01
S2
10
S3
11
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S'1
S'0
Output
Y
3-<53>
Current State
Input
Next State
Output
S1
S0
S'1
S'0
State
Encoding
S0
00
S1
01
S2
10
S3
11
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CLK
S'2
S2
S'1
S1
S'0
S0
Reset
S2
S1
S0
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S1
S'0
S0
Reset
S1
S0
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Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
Cycle 8
Cycle 9 Cycle 10
CLK
Reset
A
Moore Machine
S
??
S0
S1
S2
S2
S3
S4
S2
S3
S4
S0
S1
S2
S3
S1
S0
Mealy Machine
S
??
S0
S1
S2
S2
S3
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3-<57>
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3-<58>
Parade FSM
Unfactored FSM
P
R
Controller
FSM
TA
TB
LA
LB
Factored FSM
P
R
Mode
FSM
M
TA
TB
Lights
FSM
LA
LB
Controller
FSM
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3-<59>
R TA
Reset
P TA
S0
LA: green
LB: red
S1
LA: yellow
LB: red
R TA
R TA
S4
LA: green
LB: red
P TA
S5
LA: yellow
LB: red
R
P
S3
LA: red
LB: yellow
R TA
P TB
P TB
S2
LA: red
LB: green
R
S7
LA: red
LB: yellow
S6
LA: red
LB: green
R
R TB
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R TB
3-<60>
TA
Reset
S0
LA: green
LB: red
TA
S1
LA: yellow
LB: red
Reset
S3
LA: red
LB: yellow
S2
LA: red
LB: green
MTB
S0
M: 0
S1
M: 1
M + TB
Lights FSM
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R
Mode FSM
3-<61>
Rewrite the state transition table with the selected state encodings
Write the output table
Rewrite the combined state transition and output table with the selected
state encodings
Write Boolean equations for the next state and output logic
Sketch the circuit schematic
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Timing
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D
tsetup thold
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ta
3-<64>
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Dynamic Discipline
The input to a synchronous sequential circuit must be stable
during the aperture (setup and hold) time around the clock
edge.
Specifically, the input must be stable
at least tsetup before the clock edge
at least until thold after the clock edge
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Dynamic Discipline
The delay between registers has a minimum and
maximum delay, dependent on the delays of the circuit
elements
CLK
CLK
Q1
(a)
CL
R1
D2
R2
Tc
CLK
Q1
D2
(b)
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3-<67>
CLK
Q1
CL
D2
R1
R2
Tc
Tc
CLK
Q1
D2
tpcq
tpd
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tsetup
3-<68>
CLK
Q1
CL
D2
R1
R2
Tc
CLK
Q1
D2
tpcq
tpd
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tsetup
3-<69>
CLK
Q1
CL
D2
R1
R2
Tc
CLK
Q1
D2
tpcq
tpd
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tsetup
3-<70>
CLK
Q1
R1
CL
D2
R2
thold <
CLK
Q1
D2
tccq tcd
thold
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3-<71>
CLK
Q1
R1
CL
D2
R2
CLK
Q1
D2
tccq tcd
thold
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3-<72>
CLK
Q1
R1
CL
D2
R2
CLK
Q1
D2
tccq tcd
thold
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Timing Analysis
CLK
CLK
Timing Characteristics
tccq = 30 ps
tpcq = 50 ps
tpd =
X'
thold = 70 ps
Y'
per gate
tsetup = 60 ps
tpd = 35 ps
tcd = 25 ps
tcd =
Setup time constraint:
Tc
fc = 1/Tc =
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3-<74>
Timing Analysis
CLK
CLK
Timing Characteristics
tccq = 30 ps
tpcq = 50 ps
X'
thold = 70 ps
Y'
tpd = 3 x 35 ps = 105 ps
per gate
tsetup = 60 ps
tpd = 35 ps
tcd = 25 ps
tcd = 25 ps
Setup time constraint:
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3-<75>
CLK
tccq = 30 ps
tpcq = 50 ps
tsetup = 60 ps
tpd =
X'
Y'
thold = 70 ps
per gate
tpd = 35 ps
tcd = 25 ps
tcd =
Setup time constraint:
Tc
fc =
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3-<76>
CLK
tccq = 30 ps
tpcq = 50 ps
tsetup = 60 ps
X'
Y'
tpd = 3 x 35 ps = 105 ps
thold = 70 ps
per gate
tpd = 35 ps
tcd = 25 ps
tcd = 2 x 25 ps = 50 ps
Setup time constraint:
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3-<77>
Clock Skew
The clock doesnt arrive at all registers at the same time
Skew is the difference between two clock edges
Examine the worst case to guarantee that the dynamic discipline is
not violated for any register many registers in a system!
delay
CLK
CLK1
CLK2
Q1
R1
C
L
D2
R2
t skew
CLK1
CLK2
CLK
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3-<78>
CLK2
Q1
C
L
R1
Tc
D2
R2
CLK1
Tc
CLK2
Q1
D2
tpcq
tpd
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tsetup tskew
3-<79>
CLK2
Q1
C
L
R1
Tc
D2
R2
CLK1
CLK2
tpd
Q1
D2
tpcq
tpd
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tsetup tskew
3-<80>
CLK2
Q1
C
L
R1
Tc
D2
R2
CLK1
CLK2
Q1
D2
tpcq
tpd
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tsetup tskew
3-<81>
CLK2
Q1
R1
CLK1
CL
D2
R2
CLK2
tcd >
Q1
D2
tccq tcd
tskew thold
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3-<82>
CLK2
Q1
R1
CLK1
CL
D2
R2
CLK2
tcd >
Q1
D2
tccq tcd
tskew thold
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3-<83>
CLK2
Q1
R1
CLK1
CL
D2
R2
CLK2
Q1
D2
tccq tcd
tskew thold
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taperture
CLK
Q
Case I
D
Q
Case II
D
Q
D
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???
Case III
button
CLK
3-<85>
Metastability
Any bistable device has two stable states and a metastable state
between them
A flip-flop has two stable states (1 and 0) and one metastable state
If a flip-flop lands in the metastable state, it could stay there for an
undetermined amount of time
metastable
stable
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stable
3-<86>
Flip-flop Internals
Because the flip-flop has feedback, if Q is somewhere between 1
and 0, the cross-coupled gates will eventually drive the output to
either rail (1 or 0, depending on which one it is closer to).
R
N1
N2
: time to resolve to 1 or 0
T0, : properties of the circuit
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3-<87>
Metastability
Intuitively:
T0/Tc describes the probability that the input changes at a bad
time, i.e., during the aperture time
P(tres > t) = (T0/Tc ) e-t/
is a time constant indicating how fast the flip-flop moves away
from the metastable state; it is related to the delay through the
cross-coupled gates in the flip-flop
P(tres > t) = (T0/Tc ) e-t/
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Synchronizers
Asynchronous inputs (D) are inevitable (user interfaces,
systems with different clocks interacting, etc.).
The goal of a synchronizer is to make the probability of
failure (the output Q still being metastable) low.
A synchronizer cannot make the probability of failure 0.
CLK
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SYNC
3-<89>
Synchronizer Internals
F1
F2
Tc
CLK
D2
metastable
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tres
tsetup
tpcq
3-<90>
CLK
D2
F1
F2
Tc
CLK
D2
metastable
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tres
tsetup
tpcq
3-<91>
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3-<92>
Example Synchronizer
CLK
CLK
D2
D
F1
Suppose:
T0
Tc
= 1/500 MHz = 2 ns
Q
F2
= 200 ps
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3-<93>
Example Synchronizer
CLK
CLK
D2
D
F1
Suppose:
T0
Tc
= 1/500 MHz = 2 ns
Q
F2
= 200 ps
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3-<94>
Parallelism
Two types of parallelism:
Spatial parallelism
duplicate hardware performs multiple tasks at once
Temporal parallelism
task is broken into multiple stages
also called pipelining
for example, an assembly line
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3-<95>
Parallelism Definitions
Some definitions:
Token: A group of inputs processed to produce a group of outputs
Latency: Time for one token to pass from start to end
Throughput: The number of tokens that can be produced per unit time
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3-<96>
Parallelism Example
Ben Bitdiddle is baking cookies to celebrate the installation of
his traffic light controller. It takes 5 minutes to roll the cookies
and 15 minutes to bake them. After finishing one batch he
immediately starts the next batch. What is the latency and
throughput if Ben doesnt use parallelism?
Latency =
Throughput =
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3-<97>
Parallelism Example
Ben Bitdiddle is baking cookies to celebrate the installation of
his traffic light controller. It takes 5 minutes to roll the cookies
and 15 minutes to bake them. After finishing one batch he
immediately starts the next batch. What is the latency and
throughput if Ben doesnt use parallelism?
Latency = 5 + 15 = 20 minutes = 1/3 hour
Throughput = 1 tray/ 1/3 hour = 3 trays/hour
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3-<98>
Parallelism Example
What is the latency and throughput if Ben uses parallelism?
Spatial parallelism: Ben asks Allysa P. Hacker to help, using her own
oven
Temporal parallelism: Ben breaks the task into two stages: roll and
baking. He uses two trays. While the first batch is baking he rolls the
second batch, and so on.
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3-<99>
Spatial Parallelism
Latency:
time to
first tray
Spatial
Parallelism
10
15
Tray 1
Ben 1
Ben 1
Tray 2
Alyssa 1
Alyssa 1
20
25
30
35
40
45
50
Time
Roll
Tray 3
Ben 2
Ben 2
Tray 4
Alyssa 2
Alyssa 2
Bake
Legend
Latency =
Throughput =
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3-<100>
Spatial Parallelism
Latency:
time to
first tray
Spatial
Parallelism
10
15
Tray 1
Ben 1
Ben 1
Tray 2
Alyssa 1
Alyssa 1
20
25
30
35
40
45
50
Time
Roll
Tray 3
Ben 2
Ben 2
Tray 4
Alyssa 2
Alyssa 2
Bake
Legend
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3-<101>
Temporal Parallelism
Latency:
time to
first tray
0
10
15
20
25
30
35
40
45
50
Temporal
Parallelism
Time
Tray 1
Ben 1
Tray 2
Ben 1
Ben 2
Tray 3
Ben 2
Ben 3
Ben 3
Latency =
Throughput =
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3-<102>
Temporal Parallelism
Latency:
time to
first tray
0
10
15
20
25
30
35
40
45
50
Temporal
Parallelism
Time
Tray 1
Tray 2
Ben 1
Ben 1
Ben 2
Tray 3
Ben 2
Ben 3
Ben 3
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3-<103>