Logic Design Concepts: Zainalabedin Navabi

Chapter 2
Logic Design Concepts

Zainalabedin Navabi

Number Systems
Binary Arithmetic
Basic Logic Gates and Structures
Designing Combinational Circuits
Storage Elements
Sequential Circuit Design
Memories
Bidirectional IO
A Comprehensive Example: Serial Adder
Summary
Number Systems
Binary Arithmetic
Storage Elements
Memories
Bidirectional IO
Summary
Number Systems
Binary Numbers
Hexadecimal Numbers
Number Systems
Binary Numbers
(3256)D =
6*100 +5*101 +2*102 +3*103 = 3256
(10110)B =
0*20 +1*21 +1*22 +0*23 +1*24 = 22
A number in specified base is evaluated by considering the weight

of each digit.
Number Systems
Binary Numbers
(1101.011)B is (13.375)D
(19.7)D is (10011.101)B
The weights of binary digits on the right hand side of
binary point of a fractional binary number are 2-1, 2-2, 23, .
Number Systems
Hexadecimal Numbers
Hexadecimal Digits and Their Equivalent Decimal and Binary

Representations
7
Number Systems
Hexadecimal Numbers
(10011.101)B = (13.A)H
(11101100)B = (EC)H
Conversion from (to) a binary numbers to (from) its hexadecimal

number are straightforward processes.
Number Systems
Binary Arithmetic
Storage Elements
Memories
Bidirectional IO
Summary
Binary Arithmetic
Signed Numbers
Binary Addition
Binary Subtraction
Twos Complement System
Overflow
Fixed Point Numbers
Floating Point Numbers
10
Binary Arithmetic
Signed Numbers
(S&M)
+25 is 00011001
-25 is 10011001
Left most bit of the number represents its sign.
11
Binary Arithmetic
Binary Addition
The carry generated in each order is carried over to the next higher
order slice.
12
Binary Arithmetic
Binary Subtraction
Use Borrows
A Different Process from Binary Addition
A different hardware is needed
13
Binary Arithmetic
00011001
11100110
00000001
11100111
(=25)
(complementing all bits)
(adding a 1)
(-25)
Twos complement system simplifies signed number arithmetic.
14
Binary Arithmetic
In subtraction, A-B is done by A+(-B), in which B is twos

complement of B.
15
Binary Arithmetic
Overflow
In 2s complement system, if adding two positive (negative) numbe

results in negative (positive) number, an overflow occurs.
16
Binary Arithmetic
Overflow correction
Allocating more bits to the operators of arithmetic operations can

correct overflow.
17
Binary Arithmetic
Fixed Point Numbers
A fixed-point number has integer and fractional parts.
18
Binary Arithmetic
Sign Mantissa RadixExponent
Exponent is signed number plus 2 n-1-1

Here it is excess 127, that becomes 127-6, which is 121
19
Binary Arithmetic
A Single-Precision 32-Bit Format and a Double-Precision

64-Bit Format
20
Number Systems
Binary Arithmetic
Storage Elements
Memories
Bidirectional IO
Summary
21
Logic Value System

Logic Function Representation
Inverter
NAND and NOR gates
AND and OR gates
XOR gate
MUX gate
Three-State Gates
Look-up Tables (LUT)
Majority Function
22

Logic Value System
Four-Value Logic System
23

Inverter Gate
Inverter Gate, Its Logic Symbol, Its Algebraic Notations,

and Its Truth Table
24

NAND Gate
NAND Gate, Its Logic Symbol, Its Algebraic Notations,

and Its Truth Table
25

NOR Gate
NOR Gate, Its Logic Symbol, Its Algebraic Notations,

and Its Truth Table
26

AND and OR Gates
AND and OR Gate, Their Logic Symbol, Their Algebraic Notations,

and Their Truth Table
27

XOR Gate
XOR Gate, Its Logic Symbol, Its Algebraic Notations,

and Its Truth Table
28

MUX Gate
MUX Gate, Its Logic Symbol, Its Algebraic Notations,

and Its Truth Table
29

MUX Gate four to one
A multiplexer can be used as a switch that selects one of its

inputs depending on the binary value of its select input.
30

MUX Gate other logic gates
Multiplexer Configurations
31

MUX Gate - cascading
A 4-to-1 Multiplexer Built out of Three 2to-1 Multiplexers

32

Three-State Gates
Building a Multiplexer with Tri-state Gates

33

Look-up Tables (LUT)
Implementation of Majority Circuit using LUT
34

Logic Function Representation
Example of Logic Function with Three Inputs and One Output
35
Number Systems
Binary Arithmetic
Storage Elements
Memories
Bidirectional IO
Summary
36
Boolean Algebra
Karnaugh Maps
Dont Care Values
Minimal Coverage
Iterative Hardware
Multiplexers and Decoders
Activity Levels
Enable / Disable Inputs
A High-Level Design
37

Boolean Algebra
Involution Law
Identity Laws
Null Elements
Idempotent Laws
38

Boolean Algebra
Complementary Laws
Commutative Laws
Associative Laws
Distributive Laws
39

Boolean Algebra
Absorption Laws
Extended Absorption Laws
40

Boolean Algebra
Duality
If E is true, changing AND (.) to OR (+), OR
(+) to AND(.), 1 to 0, and 0 to 1 results in
ED that is also true.
DeMorgans Law
41

Boolean Algebra DeMorgans Example
An Overflow Detector
42

Boolean Algebra
Minimization of Boolean Expression

43

Karnaugh Maps
Boolean expressions can be shown with Karnaugh maps.
44

Karnaugh Maps
A product term of a Boolean expression corresponds to every box o

the Karnaugh map that contains a 1.
45

Karnaugh Maps
Boolean Adjacency: Two product terms are
adjacent if they consist of the same Boolean
variables and only one variable appears in its true
form in one and complement in another ( in one,
-bar in another).
Physical Adjacency: Two k-map boxes are
adjacent if they are horizontally or vertically next
to each other.
46

Karnaugh Maps
Minimization of Functions Using K-map Grouping of

Terms
47

Karnaugh Maps
Boolean manipulations correspond to the mapping of function f.
48

Karnaugh Maps
Minimizing a 4-variable Function

49

Karnaugh Maps
Combining Four Corners of

a 4-variable Map
50

Dont Care Values
51

Minimal Coverage
Implicant.
Prime Implicant.
Essential Prime Implicant.
52

Minimal Coverage
Finding Minimal Coverage
53

Iterative Hardware
An
Comparator
Iterative
54

Iterative Hardware
A Comparator Bit for a Regular

Structure
55

Iterative Hardware
The
process
of
adding
repeats for every bit position.
56

Iterative Hardware
An 8-bit Ripple Carry

Adder
57

Multiplexers and Decoders - An 8-bit 4-to-1 Mux
An 8-bit 4-to-1
Mux
58

Multiplexers and Decoders
A 4-to-1 Mux
59

Multiplexers and Decoders - A 2-to-4 Decoder
A 2-to-4 Decoder
60

Activity Levels
A NAND gate can also be looked at as an OR gate with active-low

inputs and active-high output.
61

Enable / Disable Inputs
Wiring Circuits with OE Control Inputs
62

A High-Level Design
An Absolute Value Circuit
63
Number Systems
Binary Arithmetic
Storage Elements
Memories
Bidirectional IO
Summary
64
Storage Elements
The Basic Latch

Clocked D Latch
Flip-Flops
Flip-Flop Control
Registers
65
Storage Elements
The Basic Latch
The Basic latch (Two Equivalent Circuits)
66
Storage Elements
The Basic Latch
Setting and Resetting the Basic Latch
67
Storage Elements
Clocked D Latch
When clock becomes 1, the value of D will be stored until

the next time that clock becomes 1.
68
Storage Elements
Clocked D Latch
A Quad Latch Using a Symbolic Representation of a Latch
69
Storage Elements
Flip-Flops
Edge Trigger Flip-flops
70
Storage Elements
Flip-Flops
Latch Feedback Causes Unpredictable Results
71
Storage Elements
Flip-Flops
A D-Flip-Flop, Its Structure,
Symbolic Notation and
Waveform
72
Storage Elements
Flip-Flop Control
Flip-flops with Synchronous and Asynchronous Control
73
Storage Elements
Flip-Flop Control
Clock Enabling
74
Storage Elements
Flip-Flop Control
Three-State Control
75
Storage Elements
Registers
An 8-bit register with an active-low three-state

output control and a synchronous active low reset.
76
Number Systems
Binary Arithmetic
Storage Elements
Memories
Bidirectional IO
Summary
77
Finite State Machines

Designing State Machines
Mealy and Moore Machines
One-Hot Realization
Sequential Packages
78

Finite State Machines
Huffman Model of a Sequential

Circuit
79

Problem Description - Searching for 1011
80

State Diagram for the 1011 Detector
81

State Table of the 1011 Detector

82

State Assignment
83

Transition Table for the 1011

Detector
84

Flip-Flop Excitation Tables

85

Implementing Combinational Part

86

Logic Block Diagram of the 1011 Detector

87

Mealy and Moore Machines
Mealy State Diagram
88

One-Hot Realization
One-hot Implementation
89

Sequential Packages - Counter
State Diagram of a 2-bit Counter
90

Excitation K-maps for a 2-Bit

Up-Down Counter
91

A Two-Bit Up-Down Counter
92

Two-Bit Up-Counter with Added Features

93

Sequential Packages Shift Register
A 4-bit Shift Register
94
Number Systems
Binary Arithmetic
Storage Elements
Memories
Bidirectional IO
Summary
95
Memories
Static RAM Structure
A 2n m-bit Memory
96
Memories
Static RAM Structure
SRAM Structure
97
Number Systems
Binary Arithmetic
Storage Elements
Memories
Bidirectional IO
Summary
98
Bidirectional IO
Bidirectional
Bidirectional inout lines are useful for cascading
memory chips and for reducing pin count of
memory packages.
99
Number Systems
Binary Arithmetic
Storage Elements
Memories
Bidirectional IO
Summary
100
A Comprehensive Example:
Serial Adder
Problem Statement
Design Partitioning
Datapath Design
101
Serial Adder
Problem Statement
Serial Adder Block Diagram
102
Serial Adder
Design Partitioning
Serial Adder Data/Control Partitioning

103
Serial Adder
Datapath Design
Serial Adder Datapath

104
Serial Adder
Datapath Design
Cascadable Shift-register Bit with

an Enable Input
105
Serial Adder
Serial Adder Controller
Serial Adder Controller Diagram

106
Serial Adder
Controller State Machine

Implementation
107
Serial Adder
Controller Counter Implementation

108
Number Systems
Binary Arithmetic
Storage Elements
Memories
Bidirectional IO
Summary
109
Summary
Summary
Overview
Combinational
Sequential
RT Level
Complete design flow
110

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Chapter 2

Logic Design Concepts

Logic Design Concepts

Logic Design Concepts

A number in specified base is evaluated by considering the weight

Hexadecimal Digits and Their Equivalent Decimal and Binary

Conversion from (to) a binary numbers to (from) its hexadecimal

Logic Design Concepts

Left most bit of the number represents its sign.

Twos complement system simplifies signed number arithmetic.

In subtraction, A-B is done by A+(-B), in which B is twos

In 2s complement system, if adding two positive (negative) numbe

Allocating more bits to the operators of arithmetic operations can

A fixed-point number has integer and fractional parts.

Exponent is signed number plus 2 n-1-1

A Single-Precision 32-Bit Format and a Double-Precision

Logic Design Concepts

Basic Logic Gates and Structures

Logic Value System

Basic Logic Gates and Structures

Four-Value Logic System

Basic Logic Gates and Structures

Inverter Gate, Its Logic Symbol, Its Algebraic Notations,

Basic Logic Gates and Structures

NAND Gate, Its Logic Symbol, Its Algebraic Notations,

Basic Logic Gates and Structures

NOR Gate, Its Logic Symbol, Its Algebraic Notations,

Basic Logic Gates and Structures

AND and OR Gate, Their Logic Symbol, Their Algebraic Notations,

Basic Logic Gates and Structures

XOR Gate, Its Logic Symbol, Its Algebraic Notations,

Basic Logic Gates and Structures

MUX Gate, Its Logic Symbol, Its Algebraic Notations,

Basic Logic Gates and Structures

A multiplexer can be used as a switch that selects one of its

Basic Logic Gates and Structures

Basic Logic Gates and Structures

A 4-to-1 Multiplexer Built out of Three 2to-1 Multiplexers

Basic Logic Gates and Structures

Building a Multiplexer with Tri-state Gates

Basic Logic Gates and Structures

Implementation of Majority Circuit using LUT

Basic Logic Gates and Structures

Example of Logic Function with Three Inputs and One Output

Logic Design Concepts

Designing Combinational Circuits

Designing Combinational Circuits

Designing Combinational Circuits

Designing Combinational Circuits

Designing Combinational Circuits

Designing Combinational Circuits

Designing Combinational Circuits

Minimization of Boolean Expression

Designing Combinational Circuits

Boolean expressions can be shown with Karnaugh maps.

Designing Combinational Circuits

A product term of a Boolean expression corresponds to every box o

Designing Combinational Circuits

Designing Combinational Circuits

Minimization of Functions Using K-map Grouping of

Designing Combinational Circuits

Boolean manipulations correspond to the mapping of function f.