Control Unit Design New

Introduction to CPU Design
Computer Organization
&
Assembly Language Programming
Outline
Introduction
Data Path Design
Control Unit Design
Register Transfer
Register Transfer Timing
Single Bus CPU Design
Two Bus CPU Design
Three Bus CPU Design
Hardwired Control
Microprogrammed Control
Simple CPU Design Example
Computer Organization & Assembly Language Programming
slide 2
Introduction
A CPU is decomposed into two

main parts: data path & control
unit.
Data path consists of registers,
arithmetic blocks and
interconnections.
The flow of data between
registers & arithmetic
operations are performed in
the data path.
slide 3
Introduction
Data path is controlled by a set of signals to cause

actions to take place.
Examples of such signals are
strobe signals to load registers

signals to control the connectivity of outputs to a bus.
In order to perform an operation on the data path,

it is required to generate the control signals in the
correct order to affect the correct data path
activity.
The control unit receives signals that describe the
state of the data path and the control unit sends
control signals to the data path.
slide 4
Register Transfer
The process of instruction execution can be

described as a set of register transfer operations.
In each clock, one or more register transfer
operations are performed.
Some register transfer operations cant be
implemented in one clock cycle and have to be
broken into a number of register transfer
operations that have to be performed in a
sequence.
Example: ADD AX, BX
1. Y AX
2. Z Y + BX
3. AX Z
slide 5
Single Bus CPU

The
data path is 16-bit

wide.
It consists of four general
purpose registers, R1, R2,
R3, and R4.
It contains Program
Counter (PC), Instruction
Pointer (IP), Arithmetic
&Logic Unit (ALU).
It contains Memory
Address Register (MAR)
and Memory Data
Register (MDR).
slide 6
Fetch Control Sequence
The fetch-execute process can be summarized as

follows:
1. Fetch the content of memory location pointed
by PC and load it into IR; IR [PC]
2. Increment the content of PC by 1; PC PC + 1
Instruction size is assume 1 byte for simplicity
3. Execute the instruction based on the content
of IR.
slide 7
The Wait Memory Function Complete

(WMFC) signal is activated to inform the
control unit to remain in T2 until the
memory finishes the requested read
operation.
T2 make take more than one clock cycle
depending on the number of clock cycles
needed by the memory to finish the read
operation.
After the memory finishes its function, it will
put the requested value (in this case the
instruction) in the MDR.
slide 8
Synchronous vs.
Asynchronous Memory
Data transfer between the CPU and memory can
Transfer
be either synchronous or asynchronous.

In the synchronous transfer, it is assumed that a
memory transfer operation (i.e. read or write)
can be completed in a fixed and predetermined
number of clock cycles.
In this case, whenever the CPU requests a
memory operation, it will wait for the required
number of cycles and after that it knows that the
operation has been completed.
The synchronous transfer leads to simpler
implementation, but can't accommodate devices
of widely varying speeds.
slide 9
Synchronous vs.
Asynchronous Memory
In the asynchronus transfer, the CPU after requesting
Transfer
a memory operation waits until the memory indicates
that it completed the requested operation by setting

a memory function complete signal to 1.
Fetch control sequence for both asynchronous and
synchronous memory transfer is shown. It is assumed
the memory read operation will take two clock cycles
to complete.
CpuMemInterf.s wf
slide 10
Execution Control Sequence

for Add Instruction
Consider the instruction ADD R1, [R3] (R1 R1 +

[R3])
Execution of this instruction requires the following:
1. Read the content of memory location pointed by

R3
2. Perform the addition
3. Store the result into R1
The execution control sequence for this instruction

using the single-bus CPU is:
Add1bus .s wf
slide 11

for JMP Instruction
Consider the instruction JMP Label (PC

Label)
In PC-relative addressing, what is stored in
the instruction is Label - PC.
When the CPU executes the JMP instruction, it
will add the content of PC to the offset stored
in the instruction to get the actual address of
Label, i.e. (Label-PC)+PC= Label.
The execution control sequence for the JMP
Label instruction for the single-bus CPU is:
Jmp1bus .s wf
slide 12

for Conditional JMP
consider the branch on Negative
Instruction
instruction JMPN Label (PC Label if
N=1).
Unlike unconditional Jump instruction,
conditional jump instructions perform the
jump if a condition is satisfied.
The execution control sequence for the
JMPN Label instruction for the single-bus
CPU is:
Jmpn1bus .s wf
slide 13

for Additional Instructions
ADD
R1, 2
XCHG
R1, R2
slide 14

INC [R1]
CMP R1, R2
It is assumed here that there will be a FLAGS register that will

store the flags and there will be a unit to compute the flags.
slide 15

LOOP
Next
it is assumed that the loop counter is

stored in register R1
slide 16
Performance Considerations
The execution time of a program depends on:
IC: the instruction count i.e., the number of

instructions executed in the program
CPI: the number of clocks needed for execution
per instruction
: the clock period
Execution time of a program, T= IC x CPI x

To reduce the execution time of a program:
1. Reduce number of instructions in the program.

2. Reduce number of clocks required for
executing each instruction.
3. Reduce the clock period.
slide 17
Control unit
Step A ction
1
PCout , MAR in , Read, Select4,Add, Zin
Zout , PCin , Y in , WMF C
MDRout , IR in
R3out , MAR in , Read
R1out , Y in , WMF C
MDRout , SelectY,Add, Zin
Zout , R1in , End
Figure 7.6. Control sequence

forexecutionof theinstructionAdd (R3),R1.
slide 18
Micro
instruction
PCin
PCout
MARin
Read
MDRout
IRin
Yin
Select
Add
Zin
Z out
R1out
R1 in
R3out
WMFC
End
Figure7.15 AnexampleofmicroinstructionsforFigure7.6.
slide 19
Step
Action
1
PCout , MARin , Read,Select4,Add, Zin
Zout, PCin , Yin, WMF C
MDRout , IRin
4
5
Offset-field-of-IR
out, Add, Zin
Zout, PCin , End
Figure 7.7. Control sequence for an unconditional branch instruction.
slide 20
CLK
Clock
IR
Controlstep
counter
Decoder/
encoder
External
inputs
Condition
codes
Controlsignals
Figure7.10.Controlunitorganization.
slide 21
Clock
CLK
Controlstep
counter
Reset
Stepdecoder
T 1 T2
Tn
INS1
External
inputs
INS2
IR
Instruction
decoder
Encoder
Condition
codes
INSm
Run
End
Controlsignals
Figure7.11. Separationofthedecodingandencodingfunctions.
slide 22
Branch<0
Add
T7
Branch
T5
T4
T5
End
Figure7.13. GenerationoftheEndcontrolsignal.
slide 23
Branch
T4
Add
T6
T1
Figure7.12.GenerationoftheZincontrolsignalfortheprocessorinFigure7.1.
slide 24
IR
Starting
address
generator
Clock
P C
Control
store
CW
Figure7.16. Basicorganizationofamicroprogrammedcontrolunit.
slide 25
External
inputs
IR
Clock
Startingand
branchaddress
generator
Condition
codes
PC
Control
store
CW
Figure7.18. Organizationofthecontrolunittoallow
conditionalbranchinginthemicroprogram.
slide 26
Address
Microinstruction
0
PCout , MARin , Read,Select4,Add, Zin
Zout , PCin , Yin , WMFC
MDRout , IRin
3
Branchtostartingaddressofappropriate
microroutine
. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ..
25
26
27
If N=0, then
branchtomicroinstruction0
Offset-field-of-IR
out ,SelectY, Add, Zin
Zout , PCin , End
Figure 7.17. Microroutine for the instruction Branch<0.
slide 27
Micro in structio n
F1
F2
F3
F4
F5
F1 (4 bi ts )
F2 (3bit s)
F3 (3 bi t s)
F4 (4b it s)
F5(2b i ts)
00 00 :N otran sfer
00 01 :PC
out
00 10 :MD R
out
00 11 :Zo u t
01 00 :R0o u t
01 01 :R1o u t
01 10 :R2o u t
01 11 :R3o u t
10 10 :T E MP
out
10 11 :O ffset
out
00 0:N o trans fer

00 1:PCin
01 0:IRin
01 1:Zin
10 0:R0in
10 1:R1in
11 0:R2in
11 1:R3in
00 0: No trans fer
00 1: MA Rin
01 0: MD Rin
01 1: T E MP
in
10 0: Yin
0 0 00: A dd
0 0 01: Su b
0 0: No acti on
0 1: Read
1 0: Wri te
F6
F7
F7 (1 bi t)
0 :SelectY
1 :Select4
0: No acti on
1: WMFC
16 A LU
fun cti ons
F8
F6(1b i t)
Figure7.19.
1 1 11: X OR
F8 (1bi t)
0: Co nt inu e
1: En d
An exampleofapartialformatforfieldencodedmicroinstructions.
slide 28
slide 29
Micro in struction
F0
F1
F2
F3
F0(8bits)
F1(3bits)
F2(3bi ts )
F3(3bits)
Addressofnex t
microins tru cti on
000:Notran sfer
001:PCo u t
010:MDRo ut
011:Zo u t
100:Rsrco u t
101:Rdsto u t
110:TEMPou t
000 :No t rans fer

001 :PCin
010 :IRin
011 :Zin
100 :Rs rcin
101 :Rd stin
000:Notransfer
001:MARin
010:MDRin
011:TEMP
in
100:Yin
F4
F5
F6
F7
F4(4bi ts )
F5 (2bits)
F6(1bit)
F7(1bit)
0000: Ad d
0001: Sub
00 :Noaction
01 :Read
10 :Write
0 :SelectY
1 :Select4
0 :No action
1 :W MFC
F9
F1 0
1111: XO R
F8
F8(1bi t)
F9(1bi t)
F1 0(1b it)
0:NextAdrs
1:InstDec
0:Noact io n
1:ORmo d e
0: Noaction
1: ORin d src
Figure7.23.
Formatformicroinstructionsin theexampleofSection7.5.3.
slide 30
IR
E xternal
Input s
Con diti on
codes
D ecodi ngci rcuits
AR
Cont rolstore
IR
Next address
Microins tructiondecoder
Controlsignals
Figure7.22.Microinstructionsequencingorganization.
slide 31

Control Unit Design New

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Introduction to CPU Design