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PLACEMENT
Placement is the process of placing
standard cells in the rows created at
floorplanning stage.
The goal is to minimize the total area
and interconnect cost. The quality of
routing is highly determined by the
placement.
Design goals can be timing, power
and area.
commands
placeDesign preplaceopt
placeDesign inPlacedopt no
prePlaceopt
optDesign preCTS
optDesign-preCTS incr
timeDesign prePlace
setOptmode help
setPlaceMode -help
IN PLACEMENT OPT
Re-optimizes the logic based on VR.
This can perform cell sizing, cell moving,
cell bypassing, net splitting, gate
duplication, buffer insertion, area
recovery.
Optimization performs iteration of setup
fixing, incremental timing and congestion
driven placement.
Cell padding
Cell Padding refers to placement clearance applied to std cells in PnR tools.
This is typically done to ease placement congestion or reserve some space for
future use down the flow. For example typically people apply cell padding to
the buffers/inverters used to build clock tree, so that space is reserved to insert
DECAP cells near them after CTS.
(or)
Cell padding adds hard constraints to placement. The constraints are honored
by cell legalization, CTS, and timing optimization, unless the padding is reset
after placement so those operations can use the reserved space. You can use
cell padding to reserve space for routing.
The command "specifyCellPad" is used to specify the cell padding in SOCEncounter.
This command adds padding on the right side of library cells during placement.
The padding is specified in terms of a factor that is applied to the metal2 pitch.
For example, if you specify a factor of 2, the software ensures that there is
additional clearance of two times the metal2 pitch on the right side of the
specified cells.
Reduce congestion
First analyse placed congested database, and find out the hot spot which is highly congested....
Case -1 "Congestion in Channel between macro"
Reason:- Not enough tracks is available in channels to route macro pins, or channel is highly congested
because of std cell placement.
Solution :-Need to increase channel width between Macro or pls. make sure that soft blockage or hard
blockage is properly placed.
Case -2:- "Congestion in Macro Corners"
Reason:- Corners of macro is very prone to congestion because its having connectivity from both
direction
Solution:- 1. Place some HALo around each macro (5-7um).
2. Place a hard blockage on macro corners (corner protection (Hard Placement Blockage) done after std.
cell rail creation otherwise it won't allow std cell inside it"
Case -3 "Congestion in Centre of chip/congestion in module anywhere in chip"
Reason:-Congestion in std. cell or module is based on the module local density (local density is very
high 95%-100%)
Also depend on module nature (highly connected)
Die area is less
Solution:- Module density should be even in whole chip (order os 65-85%)
use density screen/Partial blockage to control module density in specific areas.
Use cell pading
if congestion is too big in that case chip area should be increased based on the congestion fig. (it's may
be horizontal or Vertical)
No hold will check after cts becoz before cts the clock is
ideal.that means the values of the skew and slew are not
accurate. they are just the estimated values. but after cts clock
is propagated.
Also it is known that the hold violation is more dangerous than
setup violation. This is because setup violation can be fixed by
decreasing the frequency of operation of the circuit. But this is
not the case with hold. Even if the hold fix is done before the
CTS stage, the additional buffers in the clock path add up (or in
some cases reduce) certain amount of delay. Hence, it is always
recommended to fix the hold violations after the CTS stage.
checkPlace#checks placement
legality
report_timing #default it gives
setup time report(WNS).
options: > report_timing -format
{instance cell delay arrivaltime
requiredtime}, we can use -from , -to
options to know the specific paths
setup slack.