Placement

PLACEMENT
Placement is the process of placing
standard cells in the rows created at
floorplanning stage.
The goal is to minimize the total area
and interconnect cost. The quality of
routing is highly determined by the
placement.
Design goals can be timing, power
and area.

commands
placeDesign preplaceopt
placeDesign inPlacedopt no
prePlaceopt
optDesign preCTS
optDesign-preCTS incr
timeDesign prePlace
setOptmode help
setPlaceMode -help

Inputs for the PLACEMENT

STAGE
Gatelevel Netlist,
Floorplanned design and power
planning design,
Design libraries (Physical and Logical
libraries),
Design Constraints,
Technology file.

SCAIN CHAIN HANDLING

Disconnect the scan chains prior to placement to
focus on the functional critical paths.
i. If serially connected FFs are placed apart this may
require a lot more routing resources than necessary.
. If FFs are placed close together, according to their
scan chain ordering, this may hurt timing along
functional critical paths.
i. Scan chains will be reconnected after CTS
. same grouping of FFs
. Different ordering: based on placement to minimize
routing resources

IN PLACEMENT OPT
Re-optimizes the logic based on VR.
This can perform cell sizing, cell moving,
cell bypassing, net splitting, gate
duplication, buffer insertion, area
recovery.
Optimization performs iteration of setup
fixing, incremental timing and congestion
driven placement.

PPO BEFORE CTS

Before CTS performs netlist optimization
with ideal clocks.
It can fix setup, hold, max trans/cap
violations.
It can do placement optimization based
on global routing.
It re does HFN synthesis.

 the goal of pre-cts optimization is to

repair
Setup slack(WNS WORST NEGATIVE
SLACK)
Design rule violations(DRVs)
Setup times(TNS TOTAL NEGATIVE
SLACK)

PPO AFTER CTS

After CTSoptimizes timing with
propagated clock.
It tries to preserve clock skew.

What Does it mean if TNS

>>WNS?

A large TNS implies that there could be

many sub-critical violations that are
almost as bad as the critical path
violation.
It is also possible that these paths are
related or share logic.
We can verify by analyzing the subcritical paths with detailed timing
reports.

Goals for placement

optimization
Performance : Such as Timing
Logical DRCS
Routability or congestion
Area
Leakage Power

what are the reasons for routing congestion?

Routing congestion can be due to:

1. High standard cell density in small
area.
2. Placement of standard cells near
macros.
3. High pin density on one edge of
block.
4. Placing macros in the middle of
floorplan

Cell padding
Cell Padding refers to placement clearance applied to std cells in PnR tools.
This is typically done to ease placement congestion or reserve some space for
future use down the flow. For example typically people apply cell padding to
the buffers/inverters used to build clock tree, so that space is reserved to insert
DECAP cells near them after CTS.

(or)
Cell padding adds hard constraints to placement. The constraints are honored
by cell legalization, CTS, and timing optimization, unless the padding is reset
after placement so those operations can use the reserved space. You can use
cell padding to reserve space for routing.
The command "specifyCellPad" is used to specify the cell padding in SOCEncounter.
This command adds padding on the right side of library cells during placement.
The padding is specified in terms of a factor that is applied to the metal2 pitch.
For example, if you specify a factor of 2, the software ensures that there is
additional clearance of two times the metal2 pitch on the right side of the
specified cells.

Reduce congestion
First analyse placed congested database, and find out the hot spot which is highly congested....
Case -1 "Congestion in Channel between macro"
Reason:- Not enough tracks is available in channels to route macro pins, or channel is highly congested
because of std cell placement.
Solution :-Need to increase channel width between Macro or pls. make sure that soft blockage or hard
blockage is properly placed.
Case -2:- "Congestion in Macro Corners"
Reason:- Corners of macro is very prone to congestion because its having connectivity from both
direction
Solution:- 1. Place some HALo around each macro (5-7um).
2. Place a hard blockage on macro corners (corner protection (Hard Placement Blockage) done after std.
cell rail creation otherwise it won't allow std cell inside it"
Case -3 "Congestion in Centre of chip/congestion in module anywhere in chip"
Reason:-Congestion in std. cell or module is based on the module local density (local density is very
high 95%-100%)
Also depend on module nature (highly connected)
Die area is less
Solution:- Module density should be even in whole chip (order os 65-85%)
use density screen/Partial blockage to control module density in specific areas.
Use cell pading
if congestion is too big in that case chip area should be increased based on the congestion fig. (it's may
be horizontal or Vertical)

 Congestion in general referred to routing. Placement congestion is due to

overlap of standard cells, it is called overlapping rather than called as
congestion.
Routing congestion is difference between supplied and available tracks. A track
is nothing but a routing resource. Tracks fill the entire core and routing
channels are the empty space left after placing macros i.e., freezing on the
floorplan. Every tool does routing in two stages. First routing is done trial
routing which does not consider DRC rules, which gives an overall view of
routing and congested nets. After you analyze the cause for congestion in your
design, add density screen or change floorplan etc....As the Clock tree is built
and timing is freezed, the tool does the detail routing in your design. This
routing is done according to DRC and it is the final routing for your design.
Congestion reports is generated after each routing stages which shows the
difference between supplied and demanded tracks or gcells. Use routing
blockages or change placement of macros to avoid congestion.

There is Routing Congestion and it can be avoided by placing Partial

Placement Blockage around it so that the std cells are spread over and there is
no congestion and finally we can meet our timing

 Will you check HOLD timing after placement? If YES why?

If NO why?

No hold will check after cts becoz before cts the clock is
ideal.that means the values of the skew and slew are not
accurate. they are just the estimated values. but after cts clock
is propagated.

Also it is known that the hold violation is more dangerous than
setup violation. This is because setup violation can be fixed by
decreasing the frequency of operation of the circuit. But this is
not the case with hold. Even if the hold fix is done before the
CTS stage, the additional buffers in the clock path add up (or in
some cases reduce) certain amount of delay. Hence, it is always
recommended to fix the hold violations after the CTS stage.

 checkPlace#checks placement
legality
report_timing #default it gives
setup time report(WNS).
options: > report_timing -format
{instance cell delay arrivaltime
requiredtime}, we can use -from , -to
options to know the specific paths
setup slack.