1 ARM Introduction

The ARM Architecture
T
TM
1L
ARM Ltd
ARM was developed at Acron Computers ltd of Cambridge, England between

1983 and 1985.
RISC concept was introduced in 1980 at Stanford and Berkley.
Designs the ARM range of RISC processor cores
Licenses ARM core designs to semiconductor partners who fabricate and sell to
their customers.
ARM does not fabricate silicon itself
Also develop technologies to assist with the design-in of the ARM architecture
Software tools, boards, debug hardware, application software, bus architectures,

peripherals etc
39v10 The ARM Architecture
TM
ARM Partnership Model
TM
ARM Powered Products
TM
Intellectual Property
ARM provides hard and soft views to licencees
Licencees have the right to use hard or soft views of the IP
RTL and synthesis flows

Graphics Data Systems II layout (final output files for IC foundries)
soft views include gate level netlists
hard views are Data Stream Management
OEMs must use hard views
to protect ARM IP
TM
Data Sizes and Instruction Sets
The ARM is a 32-bit architecture.
When used in relation to the ARM:
Most ARMs implement two instruction sets
Byte means 8 bits

Halfword means 16 bits (two bytes)
Word means 32 bits (four bytes)
32-bit ARM Instruction Set

16-bit Thumb Instruction Set
Jazelle cores can also execute Java byte code (8-bit instructions)
TM
Processor Modes
The ARM has seven basic operating modes:
User : Normal Program execution (unprivileged mode) under which most tasks run
FIQ : Data transfer state (DMA) entered when a high priority (fast) interrupt is raised
IRQ : entered when a low priority (normal) interrupt is raised
Supervisor : Protected mode for OS, entered on reset and when a Software Interrupt
instruction is executed
Abort : used to handle memory access (data or instruction fetch) violations
Undef : used to handle undefined instructions
System : Operating System privileged mode for user (using the same registers as
user mode)
TM
The ARM Register Set

Current Visible Registers
Abort
Mode
Undef
SVC
Mode
IRQ
FIQ
User
Mode
Mode
Mode
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r15 (pc)
cpsr
spsr
Banked out Registers

User
FIQ
IRQ
SVC
Undef
Abort
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
spsr
spsr
spsr
spsr
spsr
TM
Register Organization Summary

User
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r15 (pc)
FIQ
User
mode
r0-r7,
r15,
and
cpsr
IRQ
User
mode
r0-r12,
r15,
and
cpsr
SVC
Undef
User
mode
r0-r12,
r15,
and
cpsr
User
mode
r0-r12,
r15,
and
cpsr
Abort
User
mode
r0-r12,
r15,
and
cpsr
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
spsr
spsr
spsr
spsr
spsr
Thumb state
Low registers
Thumb state
High registers
cpsr
Note: System mode uses the User mode register set

TM
The Registers
ARM has 37 registers all of which are 32-bits long.
1 dedicated program counter

1 dedicated current program status register
5 dedicated saved program status registers
30 general purpose registers
The current processor mode governs which of several banks is

accessible. Each mode can access
a particular set of r0-r12 registers

a particular r13 (the stack pointer, sp) and r14 (the link register, lr)
the program counter, r15 (pc)
the current program status register, cpsr
Privileged modes (except System) can also access
a particular spsr (saved program status register)
TM
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Registers
General Purpose registers hold either data or

address
All registers are of 32 bits
In user mode 16 data registers and 2 status

registers are visible
Data registers: r0 to r15
Three registers r13, r14, r15 perform special functions

r13: stack pointer
r14: link register (where return address is put whenever a
subroutine is called)
r15: program counter
TM
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Registers(2)
Depending upon context, register r13

and r14 can also be as GPR
Any instruction which use r0 can as well
be used with any other GPR(r1-r13)
In addition , there are two status
registers
CPSR : current program status register

SPSR : saved program status register
TM
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12
Register : r15
When
the processor is executing in ARM
state
All instructions are 32 bit wide
All instructions are word aligned
Pc value is stored in bits [31:2] with bits
[1:0] undefined
TM
13
13
Program Status Registers

31
28 27
N Z C V Q
24
23
16 15
Condition code flags
N = Negative result from ALU

Z = Zero result from ALU
C = ALU operation Carried out
V = ALU operation oVerflowed
Architecture 5TE/J only

Indicates if saturation has occurred
J bit
I F T
mode
c
I = 1: Disables the IRQ.

F = 1: Disables the FIQ.
Architecture xT only
T = 0: Processor in ARM state
T = 1: Processor in Thumb state
Mode bits
T Bit
Sticky Overflow flag - Q flag
Interrupt Disable bits.
Specify the processor mode
Architecture 5TEJ only

J = 1: Processor in Jazelle state
TM
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Processor Modes
Processor modes determine
Which registers are active, and

Access rights to CPSR register itself
Each processor mode is either
Privileged : full read-write access to the CPSR

Non-privileged : Only read access to the control field of
CPSR but read-write access to the condition flags
TM
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Processor Modes (2)
ARM has seven modes
Privileged: Abort, fast interrupt request, interrupt

request, supervisor , system and undefined
Non-privileged :User
User mode is used for programs and

applications
TM
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16
Privileged Modes
Abort: when there is a failed attempt to

access memory
Fast Interrupt Request (FIQ) & interrupt

request: correspond to interrupt levels
available on ARM
Supervisor mode: state after reset and

generally the mode in which OS kernel
executes
TM
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Privileged Modes (2)

System
mode: special version of

user mode that allows full readwrite access of CPSR
Undefined: when processor
encounters an undefined
instruction
TM
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Banked Registers
Register file contains in all 37 registers
20 registers are hidden from program at

different times
These registers are called banked registers
Banked registers are available only when the
processor is in a particular mode
Processor modes (other than system mode )
have a set of associated banked registers
that are subsets of 16 registers
Maps one-to-one onto a user mode register
TM
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SPSR
Each privileged mode (except system

mode) has associated with it a Save
Program Status Register, or SPSR.
The SPSR is used to save the state of

CPSR (Current Program status Register)
when the privileged mode is entered in
order that the user state can be fully
restored when the user process is
resumed .
TM
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Mode Changing
Mode changes by writing directly to

CPSR or by hardware when the
processor responds to exception or
interrupt.
To return to user mode a special

return instruction is used that
instructs the core to restore the
original CPSR and banked registers.
TM
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ARM memory organization

32 bit
word
aligned
for 8 and
16 bit
words also
Little
Endian
Little Endian
D0-D7 at
00
D8-D15 at 01
D16-D23 at 10
D24-D31 at 11
address
address
address
address
Big Endian
D24-D31 at
D16-D23 at
D8-D15 at
D0-D7 at
address
address
address
address
00
01
10
11
TM
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Program Counter (r15)
When the processor is executing in ARM state:
When the processor is executing in Thumb state:
All instructions are 32 bits wide

All instructions must be word aligned
Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as
instruction cannot be halfword or byte aligned).

All instructions must be halfword aligned
Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as
instruction cannot be byte aligned).
When the processor is executing in Jazelle state:

Processor performs a word access to read 4 instructions at once
TM
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Exception Handling
When an exception occurs, the ARM:
Copies CPSR into SPSR_<mode>

Sets appropriate CPSR bits
Stores the return address in LR_<mode>

Sets PC to vector address
0x0C
FIQ
IRQ
(Reserved)
Data Abort
Prefetch Abort
0x08
Software Interrupt
The current instruction is always allowed to
0x04
Undefined Instruction
complete (except in case of Reset).
0x00
Reset
Change to ARM state

Change to exception mode
Disable interrupts (if appropriate)
0x1C
0x18
To return, exception handler needs to:
0x14
Restore CPSR from SPSR_<mode>

Restore PC from LR_<mode>
0x10
This can only be done in ARM state.
IRQ is disabled on entry to all exceptions;
Vector Table
FIQ is also disabled on entry to Reset and FIQ.
Vector table can be at

0xFFFF0000 on ARM720T
and on ARM9/10 family devices
TM
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Development of the
ARM Architecture
1
2
3
Early ARM
architectures
Halfword
and signed
halfword /
byte support
System
mode
ARM7TDMI
ARM720T
5TE
CLZ
SA-110
SA-1110
Thumb
instruction
set
Improved
ARM/Thumb
Interworking
4T
ARM9TDMI
ARM940T
Saturated maths
DSP multiplyaccumulate
instructions
ARM1020E
Jazelle
5TEJ
Java bytecode
execution
ARM9EJ-S
ARM926EJ-S
ARM7EJ-S
ARM1026EJ-S
SIMD Instructions
Multi-processing
XScale
ARM9E-S
ARM966E-S
TM
V6 Memory
architecture (VMSA)
Unaligned data
support
ARM1136EJ-S
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ARM Versions
Version 1 (1983-1985): 26 bit addressing; No multiply operation; No Co-processor
Version 2 : 32 bit; Includes result multiplication co-processor
Version 3: 32 bit addressing (EX: ARM6, ARM7)
Version 4: Added signed and unsigned operations (EX: Strong ARM Intel)
Version 4T : (Thumb Mode) Embedding a 16 bit variant in a 32 bit processor (EX:
LPC21xx)
Version 5T: Superset of 4T adding new instructions.
Version 5TE : Added DSP extension. (EX: ARM9E-S)
Version 6: SIMD instructions provide greatly increased audio/video codec performance
-LDREX/STREX instructions improve multi-processing support
-VMSA (Virtual Memory System Architecture)
-Hardware and instruction set support for mixed-endianness
-1136JF-S has integral VFP coprocessor
TM
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ARM 7 Processor Core
Low end ARM core for application like

mobile phones
TDMI
T : Thumb
D : on chip debug support enabling processor to

halt in response to debug request
M : Enhanced multiplier, yield a full 64 bit result
I :Embedded ICE Hardware
Von Neumann architecture
3 stage pipeline, CPI ~ 1.9
TM
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ARM single-cycle instruction

pipeline operation
1
2
Fetch
Decode
Fetch
Execute
Decode
Fetch
Execute
Decode
Execute
3
instruction
time
TM
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3 stage Pipeline
At any time slice, 3 different instructions

may occupy each of these stages, so the
hardware in each stage has to be capable of
independent operations
When the processor is executing data

processing instructions , the latency=3
cycles and the throughout=1
instruction/cycle
When accessing r15(PC) ,r15 =address of

current instruction + 8
Before returning from exception handler
proper adjustment of lr value is required29
TM
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Pipeline Operation
Not
always cycle per instruction completion
Example : LDMIA r0,[r2,r3] (multiple

load):
-2 registers to load, instruction in execution for two
cycles
-Execution of Pre-fetched instruction

delayed Branch , Subroutine call, Exceptions
effect pipeline efficiency
TM
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Architecture Summary
32-bit RISC-processor core (32-bit instructions)
Used especially in portable devices due to low power consumption and reasonable performance (MIPS /
watt)
37 pieces of 32-bit integer registers (16 available) , uniform Register file.
Employs Load Store Architecture- Here operations operate on registers and not in memory locations
Architecture is of uniform and fixed length (instructions)
All instructions are conditional
Pipelined (ARM7: 3 stages)
Cached (depending on the implementation)
Von Neuman-type bus structure (ARM7), Harvard (ARM9)
Data can be 8-bit bytes, 16-bit half words, or 32-bit words
Words must be aligned to 4-byte boundaries (ARM),Half words must be aligned to 2-byte boundaries
(Thumb).
TM
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Enhancement to Basic RISC Features
Control over ALU and shifter for every data

processing operations to maximize their usage
Auto-increment and auto-decrement addressing
modes to optimize program loops
Load and store multiple instructions to maximize
data throughout
Conditional Execution of instruction to maximize
execution throughout
TM
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Overview: Core Data Path
Data items are placed in register file
No data processing instructions directly manipulate data in

memory.
Instructions typically use two source

registers.
A Barrel shifter on the data path can preprocess data before it enters ALU
Increment/decrement logic can update

register content for sequential access
independent of ALU
TM
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Basic ARM organization
TM
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Architecture
Architecture is characterized by Data path and
control path
No data processing takes place in memory locations
Instructions typically use 3 registers. 2 source
registers and 1 destination register.
Barrel Shifter preprocesses data, before it enters
ALU
TM
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Block Diagram
TM
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ARM Debug Architecture

Ethernet
Debugger (+ optional
trace tools)
TAP
controller
Converts debugger commands to JTAG

signals
ETM
EmbeddedICE
Logic
Embedded trace Macrocell (ETM)
Provides breakpoints and processor/system

access
JTAG interface (ICE)
Compresses real-time instruction and data

access trace
Contains ICE features (trigger & filter logic)
ARM
core
Trace port analyzer (TPA)
Captures trace in a deep buffer
Trace Port
JTAG port
EmbeddedICE Logic
TM
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ARM7TDMI-S core
TM
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Functional Diagram
TM
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JTAG Debug Port
TM
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40
JTAG & ETM
TM
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41
ARM ETM
The Embedded trace Module (ETM)

Real
Time Trace
Code coverage
Triggering
Performance analysis tool set
Extensive code verification
Software testing
TM
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System Peripherals
On
chip Flash
SRAM
Memory
External
Phase
Bus Interface (LPC22xx)
Locked Loop
Multiply external clock oscillator to provide 60 MHz

Power Control
TM
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43
Internal buses
TM
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44
Internal buses
Advanced
High Performance Bus (AHB)
Fastest way of connecting peripheral devices to the ARM core

EX: Vector Interrupt Controller (VIC)
VLSI Peripheral Bus (VPB) bridge
VPB is slower than ARM and AHB

To avoid bus contention local bus is provided fro FLASH & RAM
TM
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Memory MAP
TM
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Memory MAP
On chip Flash : 0x00000000 upward
On chip RAM: 0x 04000000 upward
FLASH Boot Loader: 0x07FFFFFFF
External Memory: 0x08000000 0x0E000000
VPB Peripherals 0x0E000000 & 0x0E020000
Four chip selects each of 16 Mbyte page
Each peripheral of 16k address space
Vector Interrupt Unit: 0xFFFFF000
TM
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Memory Accelerator Module
TM
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Memory bottleneck
ARM
CPU can go upto 80 MHz,

however on chip Flash limit speed upto
20 Mhz (50 ns)
Solution-1: As RAM is faster load critical section of the code into Ram and
execute.
Drawback : RAM is finite and precise resource
Solution-2: on-chip cache
Drawback: large portion of the LPC200 die area will be occupied
Solution-3: Memory Accelerator Module
TM
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Memory Accelerator Module
TM
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FLASH memory is split into two banks which are 128 bits wide,
independently accessed.
A single FLASH access can load 4 ARM instructions or 8

THUMB instructions
For 60 MHz ARM the number of cycles required to access the

FLASH (20 MHz) is 3 (MAM Timing register = 3)
On Reset MAM is disabled code is executed from FLASH

directly.
Partially enable the MAM to fetch sequential accessed code

from FLASH.
Finally, fully enable MAM so that it fetches all FLASH memory
TM
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ARM Code/Data Fetch
TM
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52
To help with performance analysis and also to gauge the

effectiveness
of
the
MAM,
there
are
a
group
of statistical registers which can be used to measure the
MAMs performance (to determine the instruction or data hit
rate).
TM
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Memory Map Control
First 64 bytes (0x40) may be mapped from a number of

locations, depending on the bootloader mode set in
the MEMMAP register.
MEMMAP register allows you to select between:

a. boot mode, b. FLASH mode, c. RAM mode and
External memory mode.
When selected, a new vector table will be mapped into

the first 64 bytes of memory.
For the RAM mode the contents of 0x40000000x400003F will be mapped to the start of memory
TM
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Memory Map Control
TM
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This signature is a word-wide number that is stored in the unused

location in the ARM7 vector table at 0x00000014.
The program signature is the twos compliment of the checksum of
the ARM7 vector table
TM
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Interface Signals within the processor
Clock Content
-all state changes within the processor are controlled
by mclk, the memory clock
- internal clock a mclk AND wait
- eclk clock output reflects the clock used by the core
Memory interface
-32-bit address A[31:0], bidirectional data bus
D[31:0],separate data out Dout [31:0]data in
Din [31:0]
TM
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-\mreq indicates a processor cycle
which
requires a memory access

- seq in scales that the memory address will
be sequential to that used in the previous
cycle
-lock indicates that the processor should keep
the bus to ensure the akmicity of the read
write phase of a SWAP instruction
-n\w , read or write
TM
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Interface Signals
-b[3:0], externally controlled enables on
latches on each of the 4 bytes on the data
input bus
MIMU interface
-\trans (translation control),0:user mode,
1:privileged mode
-\mode[4:0], bottom 5 bits of the CPSR(inverted)
-abort , disallow access
State
-T bit, whether the processor is currently executing ARM
or Thumb instruction
Configuration
-bigend, big-endian or little-endian
TM
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Interface Signals
TM
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Interface Signals(contd.)
Interrupt
-\fiq , fast interrupt request, higher priority

- \irq , normal interrupt request
- isync , allows the interrupt synchronizer to be
passed
Initialisation
-
\reset starts the processor from a known state ,

executing from address 00000000_(16)
TM
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ARM Memory Interface
Sequential (S cycle)
-(nMREQ , SEQ)=(0,1)
- The ARM core requests a transfer to or from an
address which is either the same , or one word or
one-half-word greater than the preceding address
Non-sequential (N cycle)
-The ARM core requests a transfer to or from an
address which is unrelated to the address used in
the preceding cycle
TM
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ARM Memory Interface(contd.)
Internal (I cycle)
- The ARM core does not require a transfer , as it
is performing an internal function , and no useful
prefetching can be performed at the same time.
Coprocessor register transfer (C cycle)

-The ARM wishes to use the data bus to
communicate with a coprocessor, but does
not require any action by the memory system.
TM
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Example ARM-based System
16 bit RAM
32 bit RAM
Interrupt
Controller
nIRQ
8 bit ROM
I/O
Peripherals
nFIQ
ARM
Core
TM
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AMBA
Arbiter
External
RAM
ARM
TIC
External
Bus
Interface
Decoder
Complete AMBA Design Kit
Interrupt
Controller
On-chip
RAM
APB
System Bus
Peripheral Bus
Advanced Microcontroller Bus

Architecture
ADK
Remap/
Pause
AHB or ASB
AMBA
Timer
Bus Interface
Bridge
External
ROM
Reset
ACT
AMBA Compliance Testbench
PrimeCell
TM
ARMs AMBA compliant peripherals
65
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Simple ARM based System
On-chip there will be an ARM core(obviously)

together with a number of system dependent
Peripherals.
Also required will be some form of interrupt

Controller which receives interrupts from the
Peripherals and raised the IRQ or FIQ input to
the ARM as appropriate.
This interrupt controller may also provide

hardware assistance for prioritizing interrupts.
TM
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Simple ARM based System

As far as memory is concerned there is likely
to be some(cheap) narrow off-chip ROM(or

flash) used to boot the system from.
There is also likely to be some 16-bit wide RAM

used to store most of the runtime data and
perhaps some code copied out of the flash.
Then on-chip there may well be some 32-bit

memory used to store the interrupt handlers
and Perhaps stacks.
TM
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TM
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68
TM
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ARM9TDMI
Harvard Architecture
Increases available memory bandwidth
- Instruction memory interface
- Data memory interface
Simultaneous access to instruction and data

memory
5 stage pipeline
Changes implemented to
increase CPI ~ 1.5
Improve maximum clock frequency
TM
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5 Stage Pipe-line Organization

Fetch
Decode
Execute
Buffer
Data
-Access data memory or buffer

Write
back
-To register file

TM
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ARM7TDMI and ARM9TDMI pipeline

comparisons
ARM7TDMI:
Fetch
Instruction Fetch
ARM9TDMI:
Decode
Thumb
De-compressor
decode
Instructi
on Fetch
read
decode
Fetch
ARM
Reg
reg
Read
write
Execute
shift ALU
Data
Shift ALU memory
access
Decode
Execute
TM
Memory
Reg
write
Write
72
72
DSP Enhancement in ARM9E
New instruction additions give architecture V5TE
New 32x16 and 16x16 multiply and multiply

accumulate instructions
SMLAxy , SMLAWy , SMLALxy, SMULWy
Allows independent access to 16-bit halves of registers
Gives efficient use of 32-bit bandwidth for packed 16bit operation
Zero overhead fractional saturating arithmetic
39v10
The ARM Architecture
QADD
, QSUB
, QDADD , QDSUB
TM
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Enhancement in 9E
Count leading zeros instruction

CLZ for faster normalisation and division
Single cycle 32x16 multiplier array
speeds up all ARM9E multiply
instructions
TM
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74
ARM v5TEJ
J:
supports implementation of Java

virtual machine
Offering
hardware and software

acceleration for optimized byte code
execution
TM
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75
ARM v6 Architecture
SIMD(single
instruction multiple data)

instructions for exploiting data
parallelism
High
code density and low power
By
slicing up the existing 32 bit data path

into four 8-bit and two 16-bit slices
Examples:QADD8<cond>
Signed
Rd, Rn , Rm
saturating 8-bit SMID add
TM
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Other features
Sum of absolute difference instructions

Example : USAD8<cond> Rd, Rm, Rs
sum of absolute difference between corresponding 8-bit
values
Dual 16 x 16 multiply
Cryptographic multiplication
A new 64+32x32 multiply accumulate

operation
Multiprocessing synchronization primitive
TM
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TM
78
78
TM
79
79
TM
80
80
TM
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Advanced Microcontroller Bus Architecture
TM
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82
TM
83
83
TM
84
84
TM
85
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TM
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TM
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1 ARM Introduction

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1 ARM Introduction

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The ARM Architecture

ARM was developed at Acron Computers ltd of Cambridge, England between

RISC concept was introduced in 1980 at Stanford and Berkley.

Designs the ARM range of RISC processor cores

ARM does not fabricate silicon itself

Software tools, boards, debug hardware, application software, bus architectures,

39v10 The ARM Architecture

ARM Partnership Model

39v10 The ARM Architecture

ARM Powered Products

39v10 The ARM Architecture

ARM provides hard and soft views to licencees

Licencees have the right to use hard or soft views of the IP

RTL and synthesis flows

OEMs must use hard views

39v10 The ARM Architecture

Data Sizes and Instruction Sets

The ARM is a 32-bit architecture.

When used in relation to the ARM:

Most ARMs implement two instruction sets

Byte means 8 bits

32-bit ARM Instruction Set

39v10 The ARM Architecture

The ARM has seven basic operating modes:

IRQ : entered when a low priority (normal) interrupt is raised

Abort : used to handle memory access (data or instruction fetch) violations

Undef : used to handle undefined instructions

39v10 The ARM Architecture

The ARM Register Set

39v10 The ARM Architecture

Banked out Registers

Register Organization Summary

Note: System mode uses the User mode register set

ARM has 37 registers all of which are 32-bits long.

1 dedicated program counter

The current processor mode governs which of several banks is

a particular set of r0-r12 registers

Privileged modes (except System) can also access

a particular spsr (saved program status register)

39v10 The ARM Architecture

General Purpose registers hold either data or

All registers are of 32 bits

In user mode 16 data registers and 2 status

Data registers: r0 to r15

Three registers r13, r14, r15 perform special functions

39v10 The ARM Architecture

Depending upon context, register r13

CPSR : current program status register

39v10 The ARM Architecture

the processor is executing in ARM

39v10 The ARM Architecture

Program Status Registers

Condition code flags

N = Negative result from ALU

Architecture 5TE/J only

I = 1: Disables the IRQ.

Sticky Overflow flag - Q flag

Interrupt Disable bits.

Specify the processor mode

Architecture 5TEJ only

39v10 The ARM Architecture

Processor modes determine

Which registers are active, and

Each processor mode is either