ECE540

COMPUTER ORGANIZATION AND

ARCHITECTURE
Register Transfer and Microoperation
bharat.sanklecha@lpu.co.in
Block 33 Room no : 203 Cabin no : 29

MICROOPERATION

An elementary operation performed during one

clock pulse, on the information stored in one or
more registers

R f(R,R)

f: shift, count, load, clear, add..

REGISTER TRANSFER LANGUAGE

Definition of organization of a computer:

1. The set of registers and their functions;

2. The sequence of microoperations;
3. The control that initiates the sequence of
microoperations

For any function of the computer, a sequence of

microoperations is used to describe it

Register transfer language

A symbolic language
A convenient tool for describing the internal
organization of digital computers
Can also be used to facilitate the design process of
digital systems.

REGISTER TRANSFER

Designation of a register

a register
Portion of a register
A bit of a register

Common ways of drawing the diagram of a register

Representation of a transfer (parallel)

R2R1
A simultaneous transfer of all bits from the source to the
destination register, during one clock pulse

Representation of a controlled (conditional) transfer

P : R2R1
A binary condition (p=1) which determines when the transfer is
to occur
If (p=1) then (R2R1)

HARDWARE IMPLEMENTATION OF
CONTROLLED TRANSFERS
Implementation of controlled transfer
P: R2R1
Block diagram

Timing diagram

Basic symbols for register Transfer

 Represent

the following conditional control

statement by two register transfer statements
with control functions:
IF (P=1) then (R1R2)
Else if (Q=1) then (R1R3)

 Show

the block diagram of the hardware

that implements the following register
transfer statement:
yT2: R2 R1, R1R2

The outputs of four registers, R0, R1, R2, and R3, are
connected through 4-to-1-line multiplexers to the
inputs of a fifth registers, R5. Each register is eight
bits long. The required transfers are dictated by four
timing variables T0 through T3 as follows:
T0: R5R0
T1: R5R1
T2: R5R2
T3: R5R3
The timing variables are mutually exclusive, which
means that only one variable is equal to 1 at any given
time, while the other three are equal to 0. Draw a block
diagram showing the hardware implementation of the
register transfers. Include the connections necessary
from the four timing variables to the selection inputs of
the multiplexers and to the load inputs of register R5.

BUS AND MEMORY TRANSFER

Paths must be provided to transfer information
from one register to another
A Common Bus System is a scheme for
transferring information between registers in a
multiple-register configuration
A bus: set of common lines, one for each bit of a
register, through which binary information is
transferred one at a time
Control signals determine which register is
selected by the bus during each particular
register transfer

BUS AND MEMORY TRANSFER

Register A Register B Register C Register D
Bus lines
Register D

Register C

Register B

Register A

3 2 1 0

3 2 1 0

3 2 1 0

3 2 1 0

D3 D2 D1 D0

C3 C2 C1 C0

B3 B2 B1 B0

A3 A2 A1 A0

D3 C3 B3 A3
3 2 1 0
MUX3

S0
S1

D2 C2 B2 A2

D1 C1 B1 A1

D0 C0 B0 A0

3 2 1 0

3 2 1 0

3 2 1 0

MUX2

S0
S1

MUX1

S0
S1

MUX0

4-Line Common Bus

S0
S1

a.
b.
c.

A digital computer has a common bus system for

16 register of 32 bits each. The bus is constructed
with multiplexers.
How many selection inputs are there in each
multiplexers.
What size of multiplexers are needed?
How many multiplexers are there in the bus?

BUS AND MEMORY TRANSFERS

The

transfer of information from a bus into one

of many destination registers is done:
By

connecting the bus lines to the inputs of all

destination registers and then:
activating the load control of the particular
destination register selected

We

write: R2 C to symbolize that the content

of register C is loaded into the register R2 using
the common system bus
It is equivalent to: BUS C, (select C)
R2 BUS (Load R2)

THREE-STATE BUS
BUFFERS

A bus system can be constructed with three-state buffer

gates instead of multiplexers
A three-state buffer is a digital circuit that exhibits
three states: logic-0, logic-1, and high-impedance (Hi-Z)

Control input C

Normal input A

Output B

Three-State Buffer

THREE-STATE BUS
BUFFERS
C=1
Buffer
A

C=0
Open Circuit
A

THREE-STATE BUS
BUFFERS
Select
Enable

S1
S0
E

0
1

24
Decoder 2

Bus line for bit 0

A0

B0

C0
Bus line with three-state
buffer (replaces MUX0 in
the previous diagram)

D0

Draw a diagram of a bus system similar to the

one shown in previous diagram, but use threestate buffers and a decoder instead of the
multiplexers.

MEMORY TRANSFER
Memory read : Transfer from memory
Memory write : Transfer to memory
Data being read or wrote is called a memory
word (called M)
It is necessary to specify the address of M when
writing /reading memory
This is done by enclosing the address in square
brackets following the letter M
Example: M[0016] : the memory contents at
address 0x0016

MEMORY TRANSFER
Assume that the address of a memory unit is
stored in a register called the Address Register
AR
Lets represent a Data Register with DR, then:
Read: DR M[AR]
Write: M[AR] DR

MEMORY TRANSFER
AR

x0C
x0E
x10
x12
x14
x16
x18

x12
R1
100
R1M[AR]

19
34
45
66
0
13
22
RAM

R1
100

R1
66

cpe 252: Computer Organization

23

a.
b.
c.

The following transfer statements specify a

memory. Explain the memory operation in each
case.
R2M[AR]
M[AR]R3
R5M[R5]

(a) Read memory word specified by the address in

AR into register R2.
(b) Write content of register R3 into the memory
word specified by the address in AR.
(c) Read memory word specified by the address in
R5 and transfer content to R5 (destroys previous
value)

MICROOPERATIONS

The microoperations most often encountered in

digital computers are classified into four
categories:
Register

transfer microoperations
Arithmetic microoperations (on numeric data stored
in the registers)
Logic microoperations (bit manipulations on nonnumeric data)
Shift microoperations

ARITHMETIC
MICROOPERATIONS
The basic arithmetic microoperations are:
addition, subtraction, increment, decrement, and
shift
Addition Microoperation:
R3 R1+R2
Subtraction Microoperation:
1s complement
R3 R1-R2 or :
R3 R1+R2+1

ARITHMETIC
MICROOPERATIONS
Ones Complement Microoperation:
R2 R2
Twos Complement Microoperation:
R2 R2+1
Increment Microoperation:
R2 R2+1
Decrement Microoperation:
R2 R2-1

Draw the circuit diagram and truth table of half

adder and full adder using basic gates.

HALF ADDER/FULL ADDER

Half Adder

Full Adder
x y
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
x
y
cn-1

x
0
0
1
1
cn-1 cn
0
0
1
0
0
0
1
1
0
0
1
1
0
1
1
1

y
0
1
0
1

c
0
0
0
1
s
0
1
1
0
1
0
0
1

s
0
1
1
0

c = xy

s = xy + xy
=x y

0 0
0 1 c
n-1
1 1
0 1

cn

x
y

0
1
0
1

1
0 c
n-1
1
0

cn = xy + xcn-1+ ycn-1
= xy + (x y)cn-1

cn

s = xycn-1+xycn-1+xycn-1+xycn-1
= x y cn-1 = (x y) cn-1

c
s

Implement four bit full adder using 1-bit full

adder?

ARITHMETIC
MICROOPERATIONS
BINARY ADDER
B3

FA

C4

B2

A3

S3

C3

B1

A2

FA

S2

C2

B0

A1

FA

S1

4-bit binary adder

(connection of FAs)

C1

A0

FA

S0

C0

Draw the block diagram for the hardware that

implements the following statements:
x+yz: ARAR+BR
where AR and BR are two n-bit registers and x,y,
and z are control variables. Include the logic
gates for the control function.

TERM PAPER Last date for submission of topic

27 Jan 2015
Last date for submission of synopsis 17 Feb
2015 (Marks :5 )

Implement 4-bit adder cum subtractor in one

circuit.

ARITHMETIC
MICROOPERATIONS
B
A
B
A
B
B
A
BINARY
ADDERSUBTRACTOR
3

FA

C4

S3

M=0 Addition
M=1 Subtraction

C3

FA

S2

C2

FA

C1

S1

4-bit adder-subtractor

A0

FA

S0

C0

Design incrementer circuit for four bit register

using half adder?

ARITHMETIC
MICROOPERATIONS
BINARY
INCREMENTER
A
A
A
A
3

HA
C

C4

S3

HA
C

S
S2

HA
C

S
S1

4-bit Binary Incrementer

1
y
HA

S
S0

ARITHMETIC CIRCUIT

Design decrementer circuit for four bit register

using full adder?

A 1 = A + 2s complement of 1 = A + 1111

ARITHMETIC
MICROOPERATIONS
ARITHMETIC CIRCUIT
A3

A2

A1

A0

1 0 B3 B3 S1 S0

1 0 B2 B2 S1 S0

1 0 B1 B1 S1 S0

1 0 B0 B0 S1 S0

3 2 1 0 S1 S0

3 2 1 0 S1 S0

3 2 1 0 S1 S0

3 2 1 0 S1 S0

41 MUX

41 MUX

41 MUX

41 MUX

Y3

Cout

FA

D3

X3

C3

Y2

FA

D2

X2

C2

Y1

FA

X1

C1

D1

4-bit Arithmetic Circuit

Y0

FA

D0

X0

Cin

ARITHMETIC CIRCUIT
This circuit performs seven distinct arithmetic
operations and the basic component of it is the
parallel adder
The output of the binary adder is calculated from
the following arithmetic sum:

D = A + Y + Cin

LOGIC MICROOPERATION
OR
AND
NOT
XOR
Other logic operation

LOGIC MICROOPERATIONS
OR Microoperation

Symbol: , +

Gate:

Example: 1001102 10101102 = 11101102

OR

OR

P+Q: R1R2+R3, R4R5 R6

ADD

LOGIC MICROOPERATIONS
AND Microoperation

Symbol:

Gate:

Example: 1001102 10101102 = 00001102

LOGIC MICROOPERATIONS
Complement (NOT) Microoperation

Symbol:

Gate:

Example: 10101102 = 01010012

LOGIC MICROOPERATIONS
XOR (Exclusive-OR) Microoperation
Symbol:

Gate:

Example: 1001102 10101102 = 11100002

OTHER LOGIC
MICROOPERATIONS
Selective-set Operation

Used to force selected bits of a register into logic1 by using the OR operation
Example: 01002 10002 = 11002
In a processor register

Loaded into a register from

memory to perform the
selective-set operation

OTHER LOGIC
MICROOPERATIONS
Selective-complement (toggling)
Operation
Used to force selected bits of a register to
be complemented by using the XOR
operation
Example:

00012 10002 = 10012

In a processor register

Loaded into a register from

memory to perform the
selective-complement
operation

OTHER LOGIC
MICROOPERATIONS
Step1:

Insert Operation

mask the desired bits

Step2: OR them with the desired value
Example:

suppose R1 = 0110 1010, and we

desire to replace the leftmost 4 bits (0110)
with 1001 then:
Step1:

0110 1010 0000 1111

Step2: 0000 1010 1001 0000

R1 = 1001 1010

OTHER LOGIC
MICROOPERATIONS
NAND Microoperation

Symbols: and

Gate:

Example: 1001102 10101102 = 11110012

OTHER LOGIC
MICROOPERATIONS
NOR Microoperation

Symbols: and

Gate:

Example: 1001102 10101102 = 00010012

OTHER LOGIC
MICROOPERATIONS

Set (Preset) Microoperation

Force all bits into 1s by ORing them with a
value in which all its bits are being assigned to
logic-1
Example: 1001102 1111112 = 1111112
Clear (Reset) Microoperation
Force all bits into 0s by ANDing them with a
value in which all its bits are being assigned to
logic-0
Example: 1001102 0000002 = 0000002

LOGIC MICROOPERATIONS
HARDWARE
TheIMPLEMENTATION
hardware implementation of logic

microoperations requires that logic gates be

inserted for each bit or pair of bits in the
registers to perform the required logic function
Most computers use only four (AND, OR, XOR,
and NOT) from which all others can be derived.

LOGIC MICROOPERATIONS
HARDWARE
IMPLEMENTATION
S
41
MUX

Ai

Bi

S0

0
1

Ei

S1

S0

Output

Operatio
n

E =A B

XOR

E =A B

OR

E =A B

AND

E=A

Complem
ent

2
3

This is for one bit i

57

LOGIC MICROOPERATIONS

SHIFT MICROOPERATIONS
Used

for serial transfer of data

Also used in conjunction with arithmetic, logic,
and other data-processing operations
The contents of the register can be shifted to
the left or to the right
As being shifted, the first flip-flop receives its
binary information from the serial input
Three types of shift: Logical, Circular, and
Arithmetic

SHIFT MICROOPERATIONS
Serial Input

rn-1

r2

r1

r0

r2

r1

r0

Serial Output

Shift Right

Determines
the shift
type
Serial Output

r3

rn-1

r3

Serial Input

Shift Left

**Note that the bit

ri is the bit at position (i) of the

register

SHIFT MICROOPERATIONS:
LOGICAL SHIFTS
Transfers 0 through the serial input
Logical Shift Right: R1shr R1

The same

Logical Shift Left: R2shl R2

The same

rn-1

r3

r2

Logical Shift Left

r1

r0

CIRCULAR SHIFTS (ROTATE

OPERATION)
Circulates the bits of the register around the two ends
without loss of information
Circular Shift Right: R1cir R1

The same

Circular Shift Left: R2cil R2

The same
rn-1

r3

r2

Circular Shift Left

r1

r0

ARITHMETIC SHIFTS
Shifts

a signed binary number to the left or

right
An arithmetic shift-left multiplies a signed
binary number by 2: ashl (00100): 01000
An arithmetic shift-right divides the
number by 2
ashr (00100) : 00010
An overflow may occur in arithmetic shiftleft, and occurs when the sign bit is
changed (sign reversal)

ARITHMETIC SHIFTS
rn-1

r3

r2

Sign
Bit

Arithmetic Shift Right

rn-1

r3

Sign
Bit

Arithmetic Shift Left

r2

r1

r1

r0

r0

ARITHMETIC SHIFTS

An overflow flip-flop Vs can be used to detect an

arithmetic shift-left overflow
Vs = Rn-1 Rn-2

Rn-1
Rn-2

Vs=

1 overflow
0 no overflow

SHIFT MICROOPERATIONS
Example:

Assume

Arithmetic

R1=11001110, then:

shift right once : R1 = 11100111

Arithmetic shift right twice : R1 = 11110011
Arithmetic shift left once : R1 = 10011100
Arithmetic shift left twice : R1 = 00111000
Logical shift right once
: R1 = 01100111
Logical shift left once
: R1 = 10011100
Circular shift right once : R1 = 01100111
Circular shift left once
: R1 = 10011101

SHIFT MICROOPERATIONS
HARDWARE
IMPLEMENTATION
A possible
choice for a shift unit would be a

bidirectional shift register with parallel load Has

drawbacks:
Needs

two pulses (the clock and the shift signal pulse)

Not efficient in a processor unit where multiple number of
registers share a common bus

It is more efficient to implement the shift operation

with a combinational circuit

SHIFT MICROOPERATIONS
HARDWARE
IMPLEMENTATION
Serial Input IR

Serial Input IL

A3A2 A1 A0

Select

MUX

MUX

MUX

MUX

H3

H2

H1

H0

4-bit Combinational Circuit Shifter

0 for shift right

1 for shift left

ARITHMETIC LOGIC SHIFT UNIT

Instead of having individual registers performing

the microoperations directly, computer systems
employ a number of storage registers connected
to a common operational unit called an
Arithmetic Logic Unit (ALU)

ARITHMETIC LOGIC SHIFT

UNIT
S3
S2
S1
S0

Ci

One stage of
arithmetic
circuit (Fig.A)

One stage
of ALU

Di
Select

Ci+1

Bi
Ai
Ai+1
Ai-1

One stage of
logic circuit
(Fig.B)

Ei

shr
shl

0
1
2
3

41
MUX

Fi

ARITHMETIC
MICROOPERATIONS
ARITHMETIC CIRCUIT
A3

A2

A1

A0

1 0 B3 B3 S1 S0

1 0 B2 B2 S1 S0

1 0 B1 B1 S1 S0

1 0 B0 B0 S1 S0

3 2 1 0 S1 S0

3 2 1 0 S1 S0

3 2 1 0 S1 S0

3 2 1 0 S1 S0

41 MUX

41 MUX

41 MUX

41 MUX

Y3

Cout

FA

D3

X3

C3

Y2

FA

D2

X2

C2

Y1

FA

X1

C1

D1

4-bit Arithmetic Circuit

Y0

FA

D0

X0

Cin

LOGIC MICROOPERATIONS
HARDWARE
IMPLEMENTATION
S
41
MUX

Ai

Bi

S0

0
1

Ei

S1

S0

Output

Operatio
n

E =A B

XOR

E =A B

OR

E =A B

AND

E=A

Complem
ent

2
3

This is for one bit i

73