XOR Gates Critical Paths Logic Layouts Transmission Gate Layouts Clocked CMOS Logic Pass Transistor Logic Standard Cells and Gate Arrays

332:479 Concepts in VLSI
Design
Lecture 14
Logic Gate Families and Layout
XOR gates
Critical Paths
Logic Layouts
Transmission Gate Layouts
Clocked CMOS Logic
Pass Transistor Logic
Standard Cells and Gate Arrays
Summary
Michael L. Bushnell -- CAIP Center and WINLAB
ECE Dept.,
RutgersinU.,
Piscataway,
NJ
April 9, 2015
Concepts
VLSI
Des
Material from: Principles of CMOS VLSI Design

By Neil E. Weste and Kamran Eshraghian
April 9, 2015
Concepts in VLSI Des
XOR Gates
nMOS XNOR gate:
CMOS XOR gate:

B
OUT
A
OUT
A
B
Complement A, B, or OUT to get an equivalence gate

April 9, 2015
Causes of Incorrect Gate

Operation
Insufficient or noisy power lines

Gate input noise
Faulty transistors
Faulty transistor connections
Incorrect transistor ratios
Charge sharing or bad clocking of dynamic gates
Ratioed and dynamic gates not used in application specific
integrated circuits (ASICs)
Used in microprocessors
April 9, 2015
Critical Paths
Slowest timing paths that limit a chips speed
Affect critical paths at these levels:
Architecture
RTL/Logic gate levels
Circuit level
Layout level
RTL/logic level pipelining, gate types, fanin & fanouts

Circuit level resize transistors to speed up
Layout level speed up by changing physical layout
False paths appear to be critical paths, but cannot propagate
transitions due to Boolean value conflicts
April 9, 2015
New Gate Notation
Bubble on transistor closest to gate output

Stage ratio increase in transistor size in successive
logic stages
Use gates with # series inputs of 2-5 for best speed
April 9, 2015
Example
April 9, 2015
Worst-Case Rise Delay for mInput NAND
April 9, 2015
Reformulation
April 9, 2015
New Delay Model
tdr = tinternal-r + k toutput-r

tinternal-r = Rp Cg m r
toutput-r = Rp Cg 1 + q (k)
n
k
tf equation is similar
Assume equal-sized n & p transistors
April 9, 2015
10
Different Delay Model
tr = t f
NAND gate: Rp = m Rn
Wp = W n
m
NOR gate: Rn = m Rp
Wn = W p
m
April 9, 2015
11
Delay of 1-3 Input Gates
April 9, 2015
12
Delay of 4-8 Input Gates
April 9, 2015
13
NAND/NOR Delays Measured

with SPICE
April 9, 2015
14
Effective Channel Resistances
April 9, 2015
15
Choice of Fastest Gate

Implementation
April 9, 2015
16
Comparison Results for Different

8-Input AND Gates
April 9, 2015
17
Logic Design Guidelines
Avoid long resistive charging / discharging paths in CMOS

Use NANDs wherever possible
Place inverters at high fanout nodes
Avoid NORs in high-speed circuits
With fanin > 4 and large fanout
Keep fanout below 5-10

Use minimum-sized gates on high fanout nodes to keep CL down
Keep rising (falling) edges sharp
When power or area is a constraint, use large fanin static gates
April 9, 2015
18
CMOS Inverter Layouts
April 9, 2015
19
High Drive Inverters
April 9, 2015
20
NAND Gate Layout Guidelines

Use metal3 or highest metal layer for power and
ground
Place transistors in complex gates:
Horizontal channels in diffusion

Vertical poly gates
Use line of diffusion rule for gate layout
April 9, 2015
21
NAND Gate Layouts
April 9, 2015
22
NOR Gate Layouts
April 9, 2015
23
Complex Logic Gate Layout
April 9, 2015
24
XNOR Layouts
April 9, 2015
25
Full-Custom Density
Improvement
1.
2.
3.
4.
Route wires over cells

Use merged source/drain connections
Use white space in sparse gates
Use smaller, optimal device sizes
April 9, 2015
26
Reducing CL
Use better physical design
April 9, 2015
27
Inferior Gate Layout
April 9, 2015
28
Superior Gate Layout

Less C on output node
April 9, 2015
29
April 9, 2015
30
Two-Input MUX
April 9, 2015
31
Two-Input MUX
April 9, 2015
32
Standard (Sandia) Cells
Fixed height (pitch)

Width varies with gate function
Automatically placed in rows and wires routed by
Cadence Envisia tool
April 9, 2015
33
Example Standard Cell
April 9, 2015
34
More Standard Cell Layouts
April 9, 2015
35
More Standard Cell Layouts
April 9, 2015
36
Gate Array (Sea of Gates) Layout
April 9, 2015
37
Sea of Gates Layout
April 9, 2015
38
Gate Array Layouts

Isolate gates from each other with vertical poly strips
tied to VSS (VDD)
April 9, 2015
39
Clocked CMOS Dynamic Logic

C2MOS Used to:
Interface with dynamic CMOS logic
Same input C as static CMOS longer tr & tf
Faster if clocking transistors at center
Better for hot e-- problems if clock transistor is next to
ground
CLOCK is last input to change
However, this defeats the isolation purpose of C2MOS
April 9, 2015
40
Clocked CMOS Logic
CLK
CLK
April 9, 2015
41
Summary
April 9, 2015
XOR gates
Critical Paths
Logic Layouts
Clocked CMOS Logic
Pass Transistor Logic
Standard Cells and Gate Arrays
42

XOR Gates Critical Paths Logic Layouts Transmission Gate Layouts Clocked CMOS Logic Pass Transistor Logic Standard Cells and Gate Arrays

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332:479 Concepts in VLSI

Material from: Principles of CMOS VLSI Design

Concepts in VLSI Des

CMOS XOR gate:

Complement A, B, or OUT to get an equivalence gate

Concepts in VLSI Des

Causes of Incorrect Gate

Insufficient or noisy power lines

Concepts in VLSI Des

RTL/logic level pipelining, gate types, fanin & fanouts

Concepts in VLSI Des

New Gate Notation

Bubble on transistor closest to gate output

Concepts in VLSI Des

Concepts in VLSI Des

Worst-Case Rise Delay for mInput NAND

Concepts in VLSI Des

Concepts in VLSI Des

New Delay Model

tdr = tinternal-r + k toutput-r

Concepts in VLSI Des

Different Delay Model

Concepts in VLSI Des

Delay of 1-3 Input Gates

Concepts in VLSI Des

Delay of 4-8 Input Gates

Concepts in VLSI Des

NAND/NOR Delays Measured

Concepts in VLSI Des

Effective Channel Resistances

Concepts in VLSI Des

Choice of Fastest Gate

Concepts in VLSI Des

Comparison Results for Different

Concepts in VLSI Des

Logic Design Guidelines

Avoid long resistive charging / discharging paths in CMOS

Keep fanout below 5-10

Concepts in VLSI Des

CMOS Inverter Layouts

Concepts in VLSI Des

High Drive Inverters

Concepts in VLSI Des

NAND Gate Layout Guidelines

Horizontal channels in diffusion

Concepts in VLSI Des

NAND Gate Layouts

Concepts in VLSI Des

NOR Gate Layouts

Concepts in VLSI Des

Complex Logic Gate Layout

Concepts in VLSI Des

Concepts in VLSI Des

Route wires over cells

Concepts in VLSI Des

Use better physical design

Concepts in VLSI Des

Inferior Gate Layout

Concepts in VLSI Des

Superior Gate Layout

Concepts in VLSI Des

Transmission Gate Layouts

Concepts in VLSI Des