Beruflich Dokumente
Kultur Dokumente
By Greg Edmiston
Scott McClure
August 2004
Tutorial Disclaimer
Enter ICFB
Type who am i
Gives
xhost address
Import the
example.v
Verilog file by
choosing File
>> Import >>
Verilog in
ICFB CIW
Open up the
Library Manger
from the CIW and
inspect to ensure
the new library
includes a cell
named
circuit_with_delay
Open the
Schematic
view of the
circuit_with_
delay from
the Library
Manager and
verify that it
resembles the
screenshot to
the left
Running Verilog XL
With the
stimcrct
highlighted
choose
Select>>Signals
Click Here
Run Button
Since the
simulation has
no initial stop
point the
output will
appear similar
to the window
to the left
To rerun the
simulation it must
first be reset
Reset the
simulation by
choosing
Reinvoke
Simulator from
the simulation
menu
Run Button
Run the
simulation by
pressing the
Run button
Simulation
output
should look
like this
Conclusion
This concludes the Verilog XL Tutorial
This tutorial was derived from the SMU
Cadence Verilog XL Tutorial
http://engr.smu.edu/~mitch/class/3381/veri
log_intro.pdf