An HDL-Based System

Design Methodologies
for Multistandard RF
SoCs
Presenter:
Jajal Jatin
141160742003

Outline
Introduction
Design Methodologies
Automated Parameter Extraction (APX)
Bluetooth Low-Energy Radio (BLE)
Understanding the Receiver
Comparison
Conclusion
Reference

Overview

Radio Frequency (RF)

Multistandard Radio
Frequency SoC
Application
Advantage

Design Approaches
Traditional Design
Approach
Drawbacks

Widely used
Limitation
HDL
Fig.1 Comparison of Design Approach [1]
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System Design With APX[1]

Testbe
Schem
nches
atics
Circuit
Des
(Daily) ign

APX

Mod
el Pa
me
Upad raH
ate DtLer& Sy
s

Matla temC &

b

Skill & Matlab

Data
Verification Engineer
Extraction

(Once)

Fig. 2 APX Characterization chart [1]

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HDL Model of BLE

HDL-based design

VCM

I=V/RIN
Laplace

Input Stage

Behaviour Stage

Output Stage

Fig. 3 The generic analog model [1]

Blocks of the Chip

Low Noise Amplifier (LNA)

Fig. 4 Analog Model implementation of the LNA [1]

Complex
Downconversion
Mixer

Fig. 5 Analog Model implementation of the Mixer [1]

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Complex Bandpass Filter

Fig. 6 Analog Model implementation of the Polyphase filter [1]

Delta Sigma ADC

Fig. 7 Analog Model implementation of the Delta sigma ADC loop [1]
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HDL Verification VS SoC Measurements

HDL Verification

Measured

LNA

Voltage Gain
Matcing (S11)
NF

20.7
-23.27 dB
3 dB

20.4
-29 dB
3.25 dB

Baseband Filter

Voltage Gain

28.54 dB

28 dB

Image Rej.

30 dB

26 dB

Frontend(LNA+Mixer
+Fiilter)

IIP3

-26.1 dBm

-28 dBm

ADC

SNR

60

56.8

Receiver

Sensitivity
NF
Max. Input
Co-Ch. Intrf.

-73 dBm
10 dBm
-10 dBm
-67 dBm

-73 dBm
11.5 dBm
-6 dBm
-67 dBm

PLL

Phase Noise
(100 kHz)
Phase Noise
(1 MHz)

-112 dBc/Hz

-109 dBc/Hz

-133 dBc/Hz

-132 dBc/Hz

21.6 mW
6.1 mW

SoC

Power-Analog
Power-Digital

Fig. 8 SoC HDL and Measurement Performance Comparison[1]

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14,000
12,000

12,099
Transistor Level

APX Analog Models

APX Event Driven Models

10,000
8,000

7,238

6,617

6,398

Seconds
6,000
4,000
2,000
257
0

2.2

CPU Time

Quadrature Delta sigma ADC

286

5.2

Elasped

264 3.76
CPU Time

290 4.16
Elasped

RF Frontend & sigma ADC

Fig. 9 Simulation times comparison[1]

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Conclusion
Automatic Parameter Extraction (APX) method enables a
fully automatic modelling of the RF and Analog blocks of an
SoC and combines the model with digital sections to get full
system verification also it assisted HDL verification saves up
to 1900x times for top level verification compared to the
transistor level verification.

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Fig. 10 Chip photo of the Bluetooth Low Energy SoC[1]

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Reference
Aytac Atac, Zhimiao Chen, Lei Liao, Yifan Wang,Marotin Schleyer, Ye
Zhang, Ralf Wunderlich, Stefan Heinen, An HDL-Based Sytstem Design
Methodology for Multistandard RF SoCs, Design Automation Conference
(DAC),51st ACM/EDAC/IEEE 2014.

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