CLASS

GRADING
HOMEWORKS
PROJECTS
REVIEW OF DIGITAL LOGIC

Digital Design using

VHDL and Verilog
Marek Perkowski
Department of Electrical and Computer Engineering
Portland State University

Introduction

Administration
About Review
RASSP Program
Why VHDL?
Flip-Flops (see ECE 271 class slides)
Shift Registers
Generalized Register
Pipelined Sorter

Administration
Instructor: Prof. Marek A. Perkowski
Course Information
My home page http://ee.pdx.edu/~mperkows
Computer Engineering web site
http://ece.pdx.edu

Administrative
Office
FAB room 160-05

Office Hours
Fridays 6 pm - 10 pm - meetings in FAB, room 150
Other Times by Appointment

Office Phone
(503)725-5411 (Answering Machine)

Administrative
Email
mperkows@ee.pdx.edu

Students with Disabilities

If you need special assistance, please inform me soon so
that we can work something out.

There is a milestone chart available on the class web

site.

Grading
HW

35%

Assignments are on the web, may be changed. If

changed, I will inform you. Usually these are miniprojects. You may be asked to present them in class.

Final Project
You will present it in class

No exams

65%

Grading
Attendance at Lecture
Not graded, but recommended.
Attendance at Friday meetings not graded, come if you
can.

Makeup Exams
Makeup homeworks or exams are not given.
Project should be completed before end of the class

Homeworks
Homeworks Require Use of VHDL
Always you have to simulate the circuit
You may be asked to synthesize it also.
Mentor Graphics Tools

contact support (cat) people

use any lab that is available. Work at home.
use addpkg
We use Modelsim for simulation and LeonardoSpectrum
for synthesis. Synthesis is mandatory for the project.

Slides
My slides are based on at least 5 books, slides from
Internet and my industrial experience, on top of
teaching this class since 1989. You can learn all you
need if you read slides in detail.
Not always I will cover all slides in class. In such
case you have to complete reading slides for this
week at home.
You can learn a lot from previous homeworks and
projects that are posted.

Required and Additional Textbooks

Required and recommended
VHDL and FPLDs. Zoran Salcic. CD ROM included.
Kluwer Academic Publishers
see my web page

Additional
The Designers Guide to VHDL

Peter J. Ashenden
Morgan-Kaufman
ISBN 1-55860-270-4 (paperback)
LOC TK7888.3.A863
Dewey Decimal 621.392--dc20
1996

Resources
IEEE Standard 1076-1993
find using search engines on WWW

Use my WWW Page resources, too much to digest.

IEEE Interactive VHDL Tutorial
On-line on Computer Engineering Home page
http://cpe.gmu.edu
password protected

Resources
Our Book
Cypress Semiconductor (Warp release 5.x)

PC-based
$99 with textbook
Oriented towards Their PLD & FPGA devices
VHDL Subset simulator

Xilinx FPGA
Student edition
Schematic, FSM, VHDL

Honor Code
You Are Encouraged to Collaborate With Other
Students in Projects.
Final VHDL code for each Homework should be
done by yourself.
In Final Project, each file should have at the top
student name of the student responsible for this part
of code.

Remind the class.

Your webpage
List of your names with interests and experiences. Previous
design projects that you have done.

Any experience in robotics?

Any experience in pipelined and systolic processors?
Any experience with image processing?
Previous VHDL or Verilog projects.
C++ experience
Other languages like LISP, Prolog, Basic, etc.
I will intentionally repeat the most important parts of material or
ideas. I believe in real understanding of material by students and
good understanding of fundamentals is most important for me.
You have to understand the combinational logic, flip-flops,
registers, state diagrams, pipelining, ALU, etc.

Homework 1
1.
2.
3.
4.
5.
6.
7.
8.

Simple Satisfiability Machine

Simple Petric Function Oracle based machine
Any type of Sorter
Fibonacci sequence generator
GCD
LCM
Any other controller from CU and DP.
Any other oracle, SEND+MORE=MONEY, graph
coloring, etc.

These are just examples, more projects will be added, you can
propose your own project.

Projects for year 2008 Transforms

1.
2.
3.
4.
5.
6.
7.
8.

Hough Transforms
Radon Transforms
Fast Fourier Transform
Hadamard
Haar
Adding
Arithmetic
Gabor

These are just examples, more projects will be added, you can
propose your own project.

Projects for year 2008 Oracles

1.
2.
3.
4.
5.
6.

Graph Coloring (optimized)

FPRM learning
Logic Puzzles
Error Correcting codes design
Traveling Salesman
Any other oracles with practical use

These are just examples, more projects will be added, you can
propose your own project.

Projects for year 2008 Cellular

Automata and Robotics
1.
2.
3.
4.
5.
6.
7.
8.
9.

Mandelbrot Set with quaternions and octonions

Robot Vision with morphological algebras
Galois Field Arithmetics for robot vision
Neural Net for a robot
PID controller for a robot
Sum of Product minimization for a robot
Decision trees in hardware for robot
Car model control
Logic Decomposition

These are just examples, more projects will be added, you can
propose your own project.

Projects for year 2008 Cellular

Automata and Robotics
1.
2.
3.
4.

Hidden Markov Model

Kalman Filter for robot
Particle Filter for robot obstacle avoidance
Genetic Algorithm in hardware

These are just examples, more projects will be added, you can
propose your own project.

Projects for year 2008 Robotics

1. Speech Recognition for a robot (new)
2. Rough Set Machine (continuation - Torrey
Lewis)
3. Convolutional Image Processor
(continuation)
4. Controller of a Robot (new)
5. Evolvable Hardware (new)
These are just examples, more projects will be added, you can
propose your own project.

Review
Mealy and
Moore
Registered
Output
Rabin-Scott

Digital System Representation

Basic Logic Functions

Logic Synthesis Using AND,

OR and NOT gates

Function Minterms and

Maxterms

Discuss
generator
of all
functions
of certain
type, use
MUX as
example

Example: 3-variable function

Example: 3-variable function

NAND, NOR, and De

Morgans Theorem

Realizing Sum of Products (SOP) using

NAND/NAND

Realizing Product of Sums

(POS) using NOR/NOR

Digital System Design: Adder

Iterative Structure of Adder

Full Adder

Full Adder
Realization

Implementation Using Multiplexers

Binary Decoder Circuits

A 2-to-4 Decoder with Enable

FA implementation using Decoders

D Flip-Flop

Sequential (Bit-Serial) Adder

Sequential Adder

Behavioral Model of Sequential Adder

To discuss on white-board
Sorting data flow
Pipelined circuit from it
Butterfly combinational circuit from it
Sequential controller from it

The concepts:

Combinational circuit
Finite State machine
Shifting circuits, starting from Moebius Counter. (Johnson)
Cooperating FSMs.
Iterative Circuit
Pipelined circuit
Systolic circuit
Cellular automaton

For students to remember

SOP and POS

Nand, Nor and De Morgan
Multiplexer
Decoder
Adder
Iterative circuit for adder
Other iterative circuits
D flip-flop
Flip-flop and register without and with enable.
Use of enable in other circuits
Sequential versus parallel circuits trade-off.

Some materials from

Alnuweiri