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Course Content
Describe instruction cycles, machine
cycles and t-states, machine cycles,
state diagram, state processor
functions, other states.
Machine Cycles
The 8085A CPU can perform seven basic machine
operations. All but the bus-idle cycle involve the transfer
of data between the CPU and a peripheral device.
The seven machine cycles are :
Opcode Fetch
Memory Read
Memory Write
IO Read
IO Write
Interrupt Ack
Bus Idle
Busses
ADDRESS
16 bits wide.
Split into two groups:
- AD0-AD7 (multiplexed with data bus)
- A8-A15
DATA BUS
8 bit
AD0-AD7
ALE (o) When this signal is logic 1 the processor specifies that
it has valid address information on the CPU pins
Example of an
Instruction Cycle
Example Instruction : STA addr
State Processor
Functions
T1 State
State Processor
Functions
T2 State
At the commencement of the T2 state the processor tristates its multiplexed bus lines AD0-AD7 when executing any
read machine cycle.
State Processor
Functions
T2 State (cont)
The processor samples the input signal RDY. If RDY is set
then the processor next enters the T3-state. If RDY is
cleared then the processor next enters the Tw-state. ( Not
shown on the simplified state transition diagram)
The processor samples the input signal HOLD. If the HOLD
input is set the processor sets an internal flip-flop, HLDA.
If the machine cycle is an opcode fetch machine cycle or if
the machine cycle is to read a program byte from memory
the program counter is incremented.
If the machine cycle is an interrupt acknowledge
machine cycle the processor asserts the INTA* control
signal instead of RD*
State Processor
Functions
T3 State
WR
For write machine cycles the processor deasserts
the
control line towards the end of the state and it is incumbent
on the external device ( memory or output port ) to use this
rising edge to latch the data, placed on the data bus during
T2, into the addressed memory or IO location.
State Processor
Functions
T3 State (cont)
State Processor
Functions
T3 State (cont)
Is this machine cycle the last machine cycle in the instruction
cycle
If no the processor enters the T1-state of the next
machine cycle
If yes and the internal INTE flip-flop is set, the processor
checks its various interrupt inputs and if one is set the
processor sets its INTA flip-flop and resets the INTE
flip-flop before proceeding to the T1-state of the next
machine cycle.
State Processor
Functions
T4 State (T5 & T6 states)
The processor only enters the T4-state for opcode fetch
machine cycles. It uses this state to decode the instruction.
For instructions which do not require any further machine
cycles for their execution, the processor also uses the T4state for instruction execution.
However, for some single byte 8085A instructions, the
single T4-state does not provide sufficient time for
instruction decoding and execution. For this class of
instruction, the processor uses two more states, T5 and T6
states, for the execution phase.
For six T-state opcode fetch machine cycles, the processor
re-samples the HOLD input during the T4-state and if
asserted sets the HLDA flip-flop.
Other States
HALT-state
The T-halt state is entered after execution of the HLT
instruction. The instruction is executed in the T4-state of
the opcode fetch machine cycle by the processor setting
the internal halt flip-flop.
In the T1 state of the next machine cycle the halt flip-flop is
tested and when found asserted the processor enters the Thalt state.
In the halt state the processor checks the hold input signal
and the interrupt inputs (provided interrupts are enabled)
If the hold input becomes asserted the processor sets the
HLDA flip-flop and then enters the hold state, where it
remains until the hold input is deasserted. Following
deassertion of the hold input the processor returns to the
halt state.
Other States
HALT-state (cont )
Other States
Wait-state
The processor can enter the T-wait state for all machine
cycles except the bus idle machine cycle.
If, during the T2-state the processor samples the RDY input in
the deasserted state, the processor enters the T-wait state at
the end of the T2-state.
In the T-wait state all bus and control signals remain as of the
end of the T2-state.
When in the T-wait state, the processor re-samples the RDY
input. If it remains de-asserted another wait state ensues
where the process is repeated. If, on the other hand, the RDY
input is found asserted the T3-state of the machine cycle is
entered.
Other States
When writing data, the processor could write data to the incorrect
memory or IO location, if sufficient time is not provided.
Other States
Hold-state
When an external device requests control of the system busses,
it does so by asserting the hold input line to the 8085A.
The hold input line is sampled by the 8085A in the T2-state, T-4
state and T-halt state and if asserted sets the hlda flip-flop.
The hlda flip-flop is tested in the last t-state of any machine
cycle and if set the processor enters the T-hold state.
The processor remains in the T-hold state whilst the hold input
remains asserted. The processor tri-states its bus drivers
effectively isolating the processor from the system and thereby
allowing an external device to have control of the system
busses.
When the hold input becomes deasserted, the processor resets
the hlda flip-flop, leaves the T-hold state and reassumes
execution of machine cycles.