Beruflich Dokumente
Kultur Dokumente
Circuits
Jan M. Rabaey
AAnantha
Design
Perspective
Chandrakasan
Borivoje Nikolic
Coping with
Interconnect
December 15, 2002
Digital Integrated Circuits2nd
Interconnect
Classes of Parasitics
Capacitive
Resistive
Inductive
Digital Integrated Circuits2nd
Interconnect
INTERCONNECT
Interconnect
CXY
Y
CY
Interconnect
CLK
In 1
In 2
In 3
CXY
CY
PDN
X
2.5 V
0V
CLK
Interconnect
0.45
0.4
X
VX
CXY
RY
0.3
Y
CY
tr
0.35
XY = RY(CXY+CY)
0.25
0.2
0.15
0.1
0.05
0
0.2
0.4
0.6
0.8
t (nsec)
Interconnect
Interconnect
Shielding
Shielding
wire
GND
V DD
Shielding
layer
GND
Substrate (GND )
Interconnect
Cc
Miller Effect
- Both terminals of capacitor are switched in opposite directions
(0 Vdd, Vdd 0)
- Effective voltage is doubled and additional charge is needed
(from Q=CV)
Digital Integrated Circuits2nd
Interconnect
Interconnect
Interconnect
Interconnect Projections
Both delay and power are reduced by dropping interconnect
Low-k
dielectrics
capacitance
Interconnect
Interconnect
V in
V out
CL
Transistor Sizing
Cascaded Buffers
Interconnect
Out
1
0.25 m process
Cin = 2.5 fF
tp0 = 30 ps
CL = 20 pF
F = CL/Cin = 8000
fopt = 3.6 N = 7
tp = 0.76 ns
(See Chapter 5)
Digital Integrated Circuits2nd
Interconnect
Area
Adriver 1 f f 2 ... f
Energy
Edriver 1 f f 2 ... f
N 1
min
N 1
C V
i
2
DD
1
F 1
Amin
Amin
f 1
f 1
F 1
C
2
2
CiVDD
L VDD
f 1
f 1
Interconnect
tp/tp0
1000
100
F = 1000
10
F = 100
11
Interconnect
Interconnect
S(ource)
G(ate)
Interconnect
GND
100 m
Out
VDD
Digital Integrated Circuits2nd
In
GND
Out
Interconnect
ESD Protection
When a chip is connected to a board, there is
unknown (potentially large) static voltage
difference
Equalizing potentials requires (large) charge
flow through the pads
Diodes sink this charge into the substrate
need guard rings to pick it up.
Interconnect
ESD Protection
V DD
PAD
D1
X
D2
C
Diode
Interconnect
Chip Packaging
Bonding wire
Chip
Mounting
cavity
L
Lead
frame
Pin
Interconnect
Pad Frame
Layout
Die Photo
Interconnect
Chip Packaging
An alternative is flip-chip:
Interconnect
Tristate Buffers
V DD
En
En
Out
Out
In
V DD
En
In
En
Interconnect
Interconnect
VDD
VDD L
Out
In
VDD L
Out
CL
driver
receiver
Interconnect
VDD
VDD
M2
M4
Bus
In1.f
M1
In2.f
Cbus
Out
M3
Cout
2.5
2
V
bus
asym
V
1.5
sym
1
0.5
0
6
time (ns)
10
12
Interconnect
INTERCONNECT
Interconnect
Impact of Resistance
We have already learned how to drive RC
interconnect
Impact of resistance is commonly seen in
power supply distribution:
IR drop
Voltage variations
Interconnect
RI Introduced Noise
VDD
f
pre
R9
VDD 2 DV9
X
M1
DV
DV
R
Interconnect
Interconnect
After
Source: Cadence
Interconnect
Power Distribution
Low-level distribution is in Metal 1
Power has to be strapped in higher layers of
metal.
The spacing is set by IR drop,
electromigration, inductive effects
Always use multiple contacts on straps
Interconnect
VDD
Logic
Logic
VDD
GND
VDD
GND
Metal 3
Metal 2
Metal 1
Courtesy Compaq
Interconnect
Metal 4
Metal 3
Metal 2
Metal 1
Courtesy Compaq
Interconnect
RP2/Vdd
Metal 4
Metal 3
RP1/Vss
Metal 2
Metal 1
Digital Integrated Circuits2nd
Courtesy Compaq
Interconnect
Electromigration (1)
Interconnect
Electromigration (2)
Interconnect
RN-1
R2
C1
C2
RN
CN-1
CN
Vin
2.5
2.5
Delay ~ L2
voltage (V)
voltage (V)
Diffused signal
propagation
x = L/4
x = L/4
1.5
1.5
1
x = L/2
x = L/2
x= L
x= L
0.5
0.5
0
x= L/10
x= L/10
00
0.5
0.5
1.5
1.5
2.5
3
2.5
3
time (nsec)
time (nsec)
3.5
3.5
4.5
4.5
Interconnect
Interconnect
Vias
Interconnect
Interconnect:
# of Wiring Layers
# of metal layers is steadily increasing due to:
= 2.2
-cm
M6
Tins
M5
S
M4
3.5
4.0
3.5
3.0
M3
3.0
2.5
2.5
2.0
M5
1.5
M4
M2
M1
1.0
M2
poly
0.5
substrate
M3
0.0
M5
2.0
M4
1.5
M1
1.0
Poly
0.5
M3
M2
M1
Poly
0.0
Interconnect
Diagonal Wiring
destination
diagonal
source
x
Manhattan
Interconnect
Using Bypasses
Driver
WL
WL
K cells
Interconnect
Reducing RC-delay
Repeater
(chapter 5)
Digital Integrated Circuits2nd
Interconnect
Interconnect
INTERCONNECT
Interconnect
L di/dt
VDD
i(t)
VDD
Vout
Vin
CL
GND
L
Interconnect
2.5
2.5
1.5
1.5
out
(V)
L di/dt: Simulation
1
0.5
0.5
0
0
0.5
1.5
2
x 10
Without inductors
With inductors
0.02
decoupled
0
0.5
1.5
1.5
2
x 10
-9
x 10
-9
x 10
-9
0.02
0.5
1.5
-9
0.5
0.5
V (V)
2
x 10
0.5
0.04
i (A)
0.04
-9
0
0
0.5
1
time (nsec)
1.5
2
x 10
-9
0.5
1
time (nsec)
1.5
Interconnect
Interconnect
Chip
Mounting
cavity
L
Lead
frame
Pin
Interconnect
Decoupling Capacitors
1
Board
wiring
Bonding
wire
Cd
SUPPLY
CHIP
2
Decoupling
capacitor
Interconnect
EV4
total effective switching capacitance = 12.5nF
128nF of de-coupling capacitance
de-coupling/switching capacitance ~ 10x
EV5
13.9nF of switching capacitance
160nF of de-coupling capacitance
EV6
34nF of effective switching capacitance
320nF of de-coupling capacitance -- not enough!
Interconnect
Interconnect
EV6 WACC
389 Signal - 198 VDD/VSS Pins
389 Signal Bondwires
395 VDD/VSS Bondwires
320 VDD/VSS Bondwires
WACC
Microprocessor
Heat Slug
587 IPGA
Interconnect
r
g
r
c
r
c
x
g
V out
g
Interconnect
R < 5 Z0
R < Z0/2
Interconnect
Should we be worried?
Interconnect
Matched Termination
Z0
Z0
ZL
Z0
Interconnect
In
VDD
Z0
s0
s1
c1
s2
c2
ZL
sn
cn
GND
Interconnect
Parallel Termination
Transistors as Resistors
V dd
Mr
Out
Vdd
Mr
Vdd
M rp
M rn
V bb
Out
Out
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0
NMOS only
PMOS only
NMOS-PMOS
PMOS with-1V bias
0.5
1
1.5
V R (Volt)
2.5
Interconnect
V
V
V DD
in
L = 2.5 nH
120
L = 2.5 nH
V in
Vs
275
Z 0 = 50
C L= 5 pF
Clamping
Diodes
V DD
1
0
Vd
Initial design
CL
4
3
L= 2.5 nH
2
in
1
0
1
0
time (sec)
Interconnect
The Network-on-a-Chip
Embedded
Processors
Memory
Sub-system
Interconnect Backplane
Accelators
Configurable
Accelerators
Peripherals
Interconnect