Field Effect

Transistors (1)

Dr. Wojciech Jadwisienczak

EE314

http://www.plasticlogic.com

Q: How we can do this?

A: A new generation of MOSFETs for plastic electronics

1.Construction of MOS
2.NMOS and PMOS
3.Types of MOS
4.MOSFET Basic Operation
5.Characteristics
6.Small-Signal Equivalent Circuits
7.Examples
Chapter 12: Field
Effect Transistors
pp. 544-577

Figure 2 -120 nm footprint T-gate with

self-aligned source and drain contacts.

Figure 4 showing the lateral etching control offered by digital recess

etching. In both micrographs, the depth of the recess is 30 nm. The
micrograph on the left shows a wide gate recess with large lateral extent
whilst the micrograph on the right shows a recess tightly defined around the
gate footprint.

http://www.three-fives.com/latest_features/webzine_features/iainthainestory.html

Building A MOSFET Transistor Using Silicon

http://micro.magnet.fsu.edu/electromag/java/transistor/index.html

It is done. Now, how does it

work?

JFET and MOSFET Transistorsor

JFET Junction Field Effect Transistor
MOSFET - Metal Oxide Semiconductor Field Effect Transistor
n-channel MOSFET & p-channel MOSFET

Symbol
L=0.1-10m
W=0.5-500m
SiO2 Thickness=0.05-0.1m
Device characteristics depend on L,W, Thickness, doping levels

n-channel MOSFET Basic Operation

Operation in the Cutoff region
pn junction:
forward
bias, reverse
bias
iD=0

for vGS<Vt0
Schematic

When vGS=0 then iD=0 until vGS>Vt0 (Vt0 threshold voltage)

n-channel MOSFET Basic Operation

Operation in the Triode Region
For viDS<vGS-Vt0 and vGS>Vt0 the NMOS is operating in the
triode region

Resistor like characteristic

(R between S & D,
Used as voltage controlled R)
For small vDS, iD is proportional
to the excess voltage vGS-Vt0

n-channel MOSFET Basic Operation

Operation in the Saturation Region (vDS is increased)

Tapering
of the
channel
iD is smaller
when
vDS is
larger

2
i D K 2 v GS Vt 0 v DS v DS

When vGD=Vt0 then the channel

thickness is 0 and
i K
D

W KP
K

L 2

vGS

Vt 0

Device parameter KP for

NMOSFET is 50 A/V2

n-channel MOSFET Basic Operation

Characteristic
Example 12.1

Channel length
modulation
id depends on vDS in
saturation region
(approx: iD =const in
saturation region)

2
i D Kv DS

p-channel MOSFET Basic Operation

It is constructed by interchanging the n and p regions of
n-channel MOSFET.
Symbol

Characteristic
How does operate
p-channel MOSFET?
-voltage polarities
-iD current
-schematic

Load-Line Analysis of NMOS Amplifier

It is a graphical analysis similar to load-line analysis of pn diode.

Schematic

We look for operating

point
vGS

vDS

Analysis
Input
loop

vGS (t ) vin (t ) VGG

vGS (t ) sin( 200t ) 4

Output
loop

V DD RD i D (t ) v DS (t )

Load
line

20 RD iD (t ) vDS (t )

Load-Line Analysis of NMOS Amplifier

Load line

20 RD iD (t ) vDS (t )

Taking iD=0 or vDS=0 we find

out the quiescent operating
point Q
The quiescent values

vGS (t ) vin (t ) VGG

vin(t)=0 then iDQ=9 mA
and vDSQ=11V
Points A & B
intersection of
curve and the
load-line

Load-Line Analysis of NMOS Amplifier

Input signal vin (t ) 1sin( 200t ) (peak-to-peak amplitude is 2V)

12V

Inverse
operation
The positive peak of the input occurs at the same time as the min.
value of vDS. These are not symmetrical sinusoids! (nonlinear distortion)

Bias Circuits
Analysis of amplifier circuits is often undertaken in two steps:
(1) The dc circuit analysis to determine the Q point. It involves the
nonlinear equation or the load-line method. This is called bias
analysis
(2) Use a linear small-signal equivalent circuit to determine circuit
parameters

The fixed-plus
self-bias circuit
Analysis

VG V DD

Equivalent
circuit

R2
R1 R2

vGS

VG vGS RS i D
Assume the VRG=0
For saturation region

i D K vGS Vt 0

v DS V DD RD RS i D

Input

Output

vDS

Bias Circuits
VG vGS RS i D

Plot of

Disregarded root

<

for vGS Vt0

Use only larger

root for vGS and
smaller for iD
Example 12.2

and

i D K vGS Vt 0