Logic Function

Optimization

Combinational Logic Circuit

Regular SOP and POS designs
Do not care expressions
Digital logic circuit applications
Karnaugh Maps
Minimization of logic functions

Combinational Logic Circuit

The function D=ABC+ABC+ABC+ABC
can be implemented in the sum of products (SOP) form as follows:

Minterm:
Product that contains
all input variables or
their complements
for which function
value is 1

Combinational Logic Circuit

The function D=(A+B+C)(A+B+C)(A+B+C)(A+B+C)
can be implemented in the product of sums (POS) form as follows:

Notice that SOP and

POS forms can be
implemented in such
regular designs for
any function.

Combinational Logic Circuit

Find canonical sum of products (SOP) form for the following
function F=AB+AC+ABC
can be implemented in the :
We have:
F=ABC+ABC+ABC+ABC+ABC

Combinational Logic Circuit

Theorem:
Each function can be represented in the unique form of
SOP or POS.
Let us obtain POS from for the following function:
D=ABC+ABC+ABC+ABC
Using DeMorgans law
D=(ABC+ABC+ABC+ABC)=
=(A+B+C)(A+B+C)(A+B+C)(A+B+C)

Two Implementations of XOR Logic Circuit

Do not Care - Logic Circuit

Do not care condition is when the output function value is not
important for a specific input combination

Do not Care - Logic Circuit

Do not care can be used to simplify the circuit
implementation

How to Design a Digital Logic Circuit?

How to translate a desired circuit functionality into a truth table?
To design a digital logic circuit to control LED display
we must first come up with a truth table.

Digital Logic Circuit Output

Decimal
Integer

Then each output ABCDEFG must

be implemented as a separate logic
function of 4 input bits xywz that
represent BCD code of integer value

BCD
xywz

ABCDEFG
segments

0000

1111110

0001

0110000

0010

1101101

0011

1111001

0100

0110011

0101

1011011

0110

0011111

0111

1110000

1000

1111111

1001

1110011

Digital Logic Circuit Output

For instance to control the
segment A the logic function is

Decimal
Integer

BCD
abcd

ABCDEFG

0000

1111110

FA=abcd+abc+abd+abc

0001

0110000

0010

1101101

or for segment B
FB=ab+abcd+abcd+abc

0011

1111001

0100

0110011

0101

1011011

0110

0011111

0111

1110000

1000

1111111

1001

1110011

Binary-Octal
Decoder Circuit
Design example

Karnaugh Maps in Logic Circuit

Karnaugh maps can be used to simplify
the logic function and its design

Karnaugh Maps in Logic Circuit

Karnaugh map uses hypercube with the same function value

in the whole cube to reduce the number of terms in the logic
function

Karnaugh Maps in Logic Circuit

The whole cube in the Karnaugh map is represented by a single

product term. For instance cubes in the example figure are.
(a) ab

(b) ab

(c) ab

Karnaugh Maps in Logic Circuit

Karnaugh Maps in Logic Circuit

Use Karnaugh maps to obtain minimum SOP for these functions:
Z=WXY+WXY+WXY+WXY
D=ABC+AB+ABC
E=ABD+ABCD+ABCD

Do not Care - Logic Circuit

1
L

F=L+DH
L
D
H

Digital Logic Circuit Output

Using Karnaugh map we can
minimize

Decimal
Integer

BCD
abcd

ABCDEFG

0000

1111110

0001

0110000

0010

1101101

0011

1111001

0100

0110011

0101

1011011

0110

0011111

0111

1110000

1000

1111111

1001

1110011

FA=abcd+abc+abd+abc
=bcd+abc+abd+abc
B
1

Output A of 7 Segments Decoder

Segment A logic function is
FA=abcd+abc+abd+abc

Decimal
Integer

BCD
abcd

ABCDEFG

0000

1111110

0001

0110000

0010

1101101

0011

1111001

0100

0110011

0101

1011011

0110

0011111

0111

1110000

1000

1111111

1001

1110011

With do not cares

FA=a+abc+bd+cb
B

Digital Logic Circuit Output

Using Karnaugh map we can
minimize
FB=ab+abcd+abcd+abc=
=bc+acd+acd+ ab
B
1

1
1
1

Decimal
Integer

BCD
abcd

ABCDEFG

0000

1111110

0001

0110000

0010

1101101

0011

1111001

0100

0110011

0101

1011011

0110

0011111

0111

1110000

1000

1111111

1001

1110011

Digital Logic Circuit Output

Using Karnaugh map we can
minimize
FB=ab+abcd+abcd+abc=
=ab+ bc+acd+acd
With do not cares
FB=cd+cd+b

Decimal
Integer

BCD
abcd

ABCDEFG

0000

1111110

0001

0110000

0010

1101101

0011

1111001

0100

0110011

0101

1011011

0110

0011111

0111

1110000

1000

1111111

1001

1110011

1
1