SERIAL COMMUNICATION CONCEPTS

By Vinayashree

BASICS
Serial communication is simple. The serial port
sends and receives bytes of information one bit at
a time.
It can be used over longer distances, as much as
1200 meters.
Serial communication implies sending data bit by
bit over a single wire.
Two ways to communicate--Synchronous and
Asynchronous

SYNCHRONOUS SERIAL
COMMUNICATION
Synchronous serial requires the clock signal to be
transmitted from the source along with the data.
Data rate for the link must be the same for the
transmitter and the receiver

Data

TRANSMITTER

1-byte wide data

clock

RECIEVER

1-byte wide data

ASYNCHRONOUS SERIAL
COMMUNICATION
Start bitindicates the beginning of the data word
Stop bitindicates the end of the data word
Parity bitadded for error detection (optional)
Data bitsthe actual data to be transmitted
Baud ratethe bit rate of the serial port
Throughputactual data transmitted per sec (total
bits transmitted-overhead)
Example: 115200 baud = 115200 bits/sec
If using 8-bit data, 1 start, 1 stop, and no parity
bits,
The throughput is: 115200 * 8 / 10 = 92160 bits/sec

ASYNCHRONOUS SERIAL
COMMUNICATION
Asynchronous transmission is easy to implement but less
efficient as it requires an extra 2-3 control bits for every 8
data bits.
With asynchronous communication, the transmitter and
receiver do not share a common clock

Remove: Start, Stop, Parity Bits

Add: Start, Stop, Parity Bits

Transmitter

1 byte-wide Data

Receiver
1 byte-wide Data

Shifts the parallel data onto the serial line

using its own clock
Also adds the start, stop, and parity check bits
Extracts the data using its own clock
Converts the serial data back to the
Parallel form after stripping
off the start, stop, and parity bits

FLOW CONTROL
RTS/CTS work together with one being the
output and the other the input. The first set of
lines are RTS (Request to Send) and CTS (Clear
to Send).
When a receiver is ready for data, it will assert
the RTS line indicating it is ready to receive data.
This is then read by the sender at the CTS input,
indicating it is clear to send the data.
The RTS/CTS lines are used for transmitting
individual packets of data.

SERDES
The basic SerDes function is made up of two functional
blocks: the Parallel In Serial Out (PISO) block (aka Parallelto-Serial converter) and the Serial In Parallel Out (SIPO)
block (aka Serial-to-Parallel converter).
There are 4 different SerDes architectures:
(1) Parallel clock SerDes,
(2) Embedded clock SerDes,
(3) 8b/10b SerDes,
(4) Bit interleaved SerDes.
The PISO (Parallel Input, Serial Output) block typically has a
parallel clock input, a set of data input lines, and input data
latches. The simplest form of the PISO has a single
shift registerthat receives the parallel data once per parallel
clock, and shifts it out at the higher serial clock rate.

SERDES

The SIPO (Serial Input, Parallel Output) block

typically has a receive clock output, a set of data
output lines and output data latches.
The SIPO block then divides the incoming clock
down to the parallel rate. Implementations
typically have two registers connected as a double
buffer. One register is used to clock in the serial
stream, and the other is used to hold the data for
the slower, parallel side.

PCI EXPRESS

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PCI Express(Peripheral Component Interconnect

Express), officially abbreviated asPCIe, is a high-speed
serialcomputerexpansion busstandard designed to
replace the olderPCI,PCI-X, andAGPbus standards.
PCIe has numerous improvements
higher maximum system bus throughput,
lower I/O pin count and smaller physical footprint,
better performance scaling for bus devices,
a more detailed error detection and reporting
mechanism.
Nativehot-plugfunctionality.
I/O virtualization.

PCI EXPRESS
It follows point to point Bus topology as opposed to shared bus
topology used by PCI
Each device in the system has direct and exclusive access to the
switch. In other words, each device sits on its own dedicated bus,
which in PCIe lingo is called a link.
With a switched fabric, the switch makes all the resource-sharing
decisions.By centralizing the traffic-routing and resourcemanagement
functions in a single unit,
PCIe also enables another
important and long
overdue next-generation
function: quality of service
(QoS).

LINK:
a connection between two a PCIe device and a PCIe switch is
called a link.
Each link is composed of one or more lanes, and each lane is
capable of transmitting one byte at a time in both directions at
once. This full-duplex communication is possible because each
lane is itself composed of one pair of signals: send and receive.
In order to transmit PCIe packets, which
are composed of multiple bytes, a one-lane
link must break down each packet into a
series of bytes, and then transmit the bytes
in rapid succession. The device on the
receiving end must collect all of the bytes
and then reassemble them into a complete
packet.

PCI EXPRESS FABRIC TOPOLOGY

A Root Complex (RC) denotes the root of an I/O
hierarchy that connects the CPU/memory
subsystem to the I/O.
Endpoint refers to a type of Function that can be
the Requester or Completer of a PCI Express
transaction either on its own behalf or on behalf
of a distinct non-PCI Express device (other than a
PCI device or Host CPU.
A PCI Express to PCI/PCI-X Bridge provides a
connection between a PCI Express fabric and a
PCI/PCI-X hierarchy.

PCI EXPRESS

PCI EXPRESS LAYERING

OVERVIEW
PCI Express can be divided into three discrete
logical layers: the Transaction Layer, the Data
Link Layer, and the Physical Layer.
Each of these layers is
divided into two sections:
one that processes outbound
(to be transmitted)
information and one that
processes inbound (received)
information.

TRANSACTION LAYER
This is the top layer that interacts with the software above.
Functions of Transaction Layer:
1. Mechanisms for differentiating the ordering and processing
requirements of Transaction Layer Packets (TLPs)
2. Credit-based flow control
3. TLP construction and processing
4. Association of transaction-level mechanisms with device
resources including Flow Control and Virtual Channel
management

DATA LINK LAYER

The Data Link Layer acts as an intermediate
stage between the Transaction Layer and the
Physical Layer. Its primary responsibility is to
provide a reliable mechanism for exchanging
Transaction Layer Packets (TLPs) between the
two components on a Link.

CONT..
The Data Link Layer performs three vital services for the PCIe express link:
sequence

the transaction layer packets (TLPs) that are generated by the transaction layer,
ensure reliable delivery of TLPs between two endpoints via an acknowledgement protocol (ACK
andNAKsignaling) that explicitly requires replay of unacknowledged/bad TLPs,
initialize

and manage flow control credits.

the transmit side, the data link layer generates an incrementing sequence number for each
outgoing TLP. It serves as a unique identification tag for each transmitted TLP, and is inserted
into the header of the outgoing TLP. A 32-bitcyclic redundancy checkcode (known in this
context as Link CRC or LCRC) is also appended to the end of each outgoing TLP.
On the receive side, the received TLP's LCRC and sequence number are both validated in the
link layer. If either the LCRC check fails (indicating a data error), or the sequence-number is
out of range (non-consecutive from the last valid received TLP), then the bad TLP, as well as
any TLPs received after the bad TLP, are considered invalid and discarded. The receiver sends
a negative acknowledgement message (NAK) with the sequence-number of the invalid TLP,
requesting re-transmission of all TLPs forward of that sequence-number. If the received TLP
passes the LCRC check and has the correct sequence number, it is treated as valid. The link
receiver increments the sequence-number (which tracks the last received good TLP), and
forwards the valid TLP to the receiver's transaction layer. An ACK message is sent to remote
transmitter, indicating the TLP was successfully received (and by extension, all TLPs with past
sequence-numbers.)
On

PHYSICAL LAYER

The PCIe Physical Layer specification is divided into two sublayers, corresponding to electrical and logical specifications.
The logical sub layer is sometimes further divided into a MAC
sub layer and a PCS, although this division is not formally part
of the PCIe specification. The PIPE specification also identifies
thephysical media attachment(PMA) layer, which includes the
serializer/deserializer (SerDes)and other analog circuitry

At the electrical level, each lane consists of two unidirectional

LVDSorPCMLpairs at 2.525Gbit/s. Transmit and receive are
separate differential pairs, for a total of four data wires per
lane.
A slot of a large physical size (e.g., 16) can be wired electrically
with fewer lanes (e.g., 1, 4, 8, or 12) as long as it provides
the ground connections required by the larger physical slot size.