UVM REG Migration Plan

Aug 2013

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OVM/UVM RGM Generation Flow

Autoreg
Golden
Source

.blk
.blk
Autoreg Perl Wrapper

Autoreg

PAPI
Generators

PAPI

Visualization

Document

RTL

Legacy

HDL Headers

SW/FW

Vera

UVM RGM

.html

.mif

.v

FLAT
file

.vh

.h

.vri
.vri

.vr
.sv

.vhd

.asm

.vri
.vr

.html

Delta
Report

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UVM REG Generation Flow

Leverage existing UVM generators from vendors
Intercept vendor generators with IP-XACT XMLs to make SCALe solution vendor-neutral
Generate IP-XACT from Scale (Autoreg version 1.9)
Use reg gen scripts from Cadence(IREGGEN) or Synopsys(RALGEN) to generate UVM
REG.
Added the support for Synopsys script, Autoreg itself generates the Data base file for
Synopsys.
Generated code can be used with any simulator.

.seq

.blk
.blk

Autoreg

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Autoreg
Golden
Source

IP-XACT
XML

Vendor UVM
Generator

UVM Sequence

UVM REG/RAL

.vr
.sv

.vr
.sv

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Autoreg
Perl
Wrapper

Why UVM REG

Industry Accellera standard
Vendor neutral.
Vendors are moving to UVM REG and dropping custom solutions like
RGM
Better architecture than RGM and more functionality

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Supported Features
Array register
User-specified address interval stride per index increment
Non-zero start index
2-D array
Read-write conjugates (twin register, overlap)
Same address but separate storages
One is read-only and the other one is write-only
Write-1-to-clear , RTC , WITS
Write 1 to certain bit field to clear the bit field or the entire parent register
Similar support for write-0-to-clear, read-to-clear
Exclude registers from standard test sequence :csrsetting
Exclude read and/or write accesses
Exclude selected registers and/or bit fields
Exclude from certain test, e.g. alias, reset, etc.
Banked registers
Same address but separate storages
Controlled by an external signal
UVM base class library support for banked registers

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Non supported Registers

Mode-dependent register
Same address and same storage
Bit field and enum definitions change
Controlled by a bit field from the same register or another register
Register Aliasing
Same register (same storage) accessible from different address offsets
Indirect registers
SW only accesses a control register which contains index field and data field
Indirect access to shadow (indirect) registers based on the index and data fields of the control
register
Shadow registers not accessible by SW
Double-buffer registers
A pair of registers: front-end and shadow
SW writes to the front-end register only
HW reads from the shadow register only
An external signal latches data from front-end register to the shadow register
Retention Register

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IP-XACT support and Vendor Extensions

Scale IP-XACT supports vendor extensions for below features in cadence
define format:
Array registers
Overlap registers
Banked registers
Field access events (W1TC, W1TS, RTC)
Exclude registers/fields from tests (CSR)
Scale IP-XACT supports vendor extensions for below features in
Synopsys define format:
Array registers(Multi Dimensional Array Registers)
Overlap registers
Banked registers
Linear stride index in IPXACT

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IP-XACT Examples
For Bank registers
<spirit:vendorExtensions>
<vendorExtensions:bank>secure</vendorExtensions:bank>
<vendorExtensions:overlap>true</vendorExtensions:overlap>
</spirit:vendorExtensions>

For Array Registers

<spirit:vendorExtensions>
<vendorExtensions:array>
<vendorExtensions:x_from>0</vendorExtensions:x_from>
<vendorExtensions:x_to>3</vendorExtensions:x_to>
<vendorExtensions:offset_calc>'h110+'h4*x</vendorExtensions:offset_calc>
<vendorExtensions:hdl_pattern>("BLK_ARR2_%0d%0d%0d", x)
<vendorExtensions:hdl_pattern>
</vendorExtensions:array>
</spirit:vendorExtensions>

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How to Generate UVM REG (Cadence)

Use SCALe Autoreg version 2.1

setenv AUTOREG_VERSION 2.1

Generate IP-XACT from Autoreg

Autoreg <blk file> -gen_ipxact cadence -gen_qcsr ARM

This will generate IP-XACT (xml) file.

Set the path of UVM_HOME and IREG_GEN and use ireggen script as below

$IREG_GEN/bin/iregGen \
-i <IP-XACT file> \
-d output_ireggen \
-pkg my_pkg -ta _t -nc

This will generate UVM REG files.

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How to Generate UVM REG

Use SCALe Autoreg version 2.1

setenv AUTOREG_VERSION 2.1

Generate IP-XACT from Autoreg

Autoreg <blk file> -gen_ipxact synopsys -gen_qcsr ARM
This will generate IP-XACT(xml) file and UVM REG files too.
No need to generate UVM REG files separately for Synopsys as Autoreg calls ralgen scripts
internally and generates the UVM REG files
Complete working example is available at

/prj/iceng/SCALe/release/examples/integartion_and_simulation/uvm_reg/

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UVM REG Access APIs

write()/read(): Write/read immediate value to DUT.
set()/get() : Sets or gets mirrored/shadow-registers value.
randomize() : Using the randomize() method copies the
randomized value in the uvm_reg_field::value property into the
desired value of the mirror by the post_randomize() method.
update()
: Invokes the write() method if the desired value
(previously modified using set() or randomize()) is different from
the mirrored value.
mirror()
: Invokes the read() method to update the mirrored
value based on the readback value. mirror() can also compare
the readback value with the current mirrored value before
updating it.

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Example of Register Sequences

class blk_seq extends uvm_reg_sequence;
my_regfile model;
`uvm_object_utils(blk_seq)
function new ( string name=blk_seq );

Pointer to the register model container

super.new(name);
Note that there are read/write
tasks that cover the do items

endfunction : new
virtual task body();
uvm_status_e status;
int data;
model.config.write(status, h12, .parent(this));

Frontdoor Write

model.config.write(status, h34, UVM_BACKDOOR, .parent(this));

Backdoor Write

model.config.read(status, data, UVM_BACKDOOR, .parent(this));

Backdoor Read

model.my_mem.write(status, h8, h1234_5678, .parent(this));

Memory frontdoor

void'(model.randomize());
model.update(status, UVM_BACKDOOR, .parent(this));
model.mirror(status, UVM_CHECK, UVM_BACKDOOR, .parent(this));

Container level
Backdoor update

endtask : body
endclass : blk_seq
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Container level
Backdoor mirror

More Information on SCALe

SCALe Wiki
go/scale
Includes FAQ, documentation, training, examples, and link to eRoom
SCALe email lists
scale.users
User email list.
Receive notification emails for new releases.
This email list also controls eRoom access.
scale.help
Open an RT ticket to ask for help with tool.

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Thank You
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INTERNAL USE ONLY

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