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# THE INVERTER

DYNAMICS

## [Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]

EE415 VLSI Design

Inverter Dynamics
Dynamic Behavior
Delay Definitions
Voltage Transfer Characteristic
Switching Threshold
Propagation Delay
Transient Response
Inverter Sizing
Power Dissipation
Short Circuit Currents
Technology Scaling
EE415 VLSI Design

Dynamic Behavior
Propagation Delay, Tp
Defines how quickly output is affected by input
Measured between 50% transition from input to
output
tpLH defines delay for output going from low to high
tpHL defines delay for output going from high to low
Overall delay, tp, defined as the average of tpLH and
tpHL
EE415 VLSI Design

Dynamic Behavior
Rise and fall time, Tr and Tf
Defines slope of the signal
Defined between the 10% and 90% of the
signal swing
Propagation delay and rise and fall times
affected by the fan-out due to larger
EE415 VLSI Design

Delay Definitions
Vin

50%
t
t
Vout

t
pLH

pHL

90%
50%
10%

tf
EE415 VLSI Design

tr

## The Ring Oscillator

A standard method is needed to measure the
gate delay
It is based on the ring oscillator
2Ntp >> tf + tr for proper operation

## EE415 VLSI Design

Ring Oscillator
v1

v0

v0

v2

v1

v3

v4

v5

T = 2 tp N
EE415 VLSI Design

v5

Voltage
Transfer
Characteristi
c

Characteristics
VDD

S
D

Vin

Vout
CL

D
G
S

## EE415 VLSI Design

VDD

IDn

V in = V DD +VGSp
IDn = - IDp
V out = VDD +VDSp

S
D

Vin

Vout

Vout
IDp

CL

D
G
Vin=0

IDn

IDn

V in=3

VGSp=-2
VGSp=-5

V DSp
Vin = V DD+VGSp
IDn = - IDp

Vin=0
Vin=3

VDSp

Vout = V DD+VDSp

Vout

IDn (A)

PMOS

NMOS

X 10-4

Vin = 0V

Vin = 2.5V

Vin = 0.5V

Vin = 2.0V

Vin = 1.0V

## Vin = 1V Vin = 1.5V

Vin = 0.5V

Vin = 2V

Vin = 1.5V

Vin = 1.0V
Vin = 0.5V

Vin = 1.5V
Vin = 2.0V

Vin = 2.5V

Vout (V)

Vin = 0V

0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V
EE415 VLSI Design

## CMOS Inverter VTC

NMOS off
PMOS res

Vout (V)

NMOS sat
PMOS res

NMOS sat
PMOS sat

NMOS res
PMOS sat

Vin (V)
EE415 VLSI Design

NMOS res
PMOS off

Cutoff

Linear

Saturation

pMOS

## Vin -VDD= VGS> VT

Vin -VDD=VGS< VT

Vin -VDD=VGS> VT

Vin -Vout=VGD< VT

Vin -Vout=VGD>VT

nMOS

Vin = VGS< VT

Vin =VGS> VT

Vin =VGS> VT

## Vin -Vout =VGD< VT

VDD

Regions of operations
For nMOS and pMOS
V
In CMOS inverter

S
D

in

Vout

D
G
S
EE415 VLSI Design

CL

For valid dc operating points:
current through NMOS = current through
PMOS
=> dc operating points are the intersection of
All operating points located at high or low
output levels
=> VTC has narrow transition zone
high gain of transistors during switching
transistors in saturation
EE415 VLSI Design

## high transconductance (gm)

Switching Threshold

## VM where Vin = Vout (both PMOS and NMOS in

saturation since VDS = VGS)
VM rVDD/(1 + r) where r = kpVDSATp/knVDSATn
Switching threshold set by the ratio r, which
compares the relative driving strengths of the PMOS
and NMOS transistors
Want VM = VDD/2 (to have comparable high and low
noise margins), so want r 1
(W/L)p = knVDSATn(VM-VTn-VDSATn/2)
(W/L)n kpVDSATp(VDD-VM+VTp+VDSATp/2)

## In 0.25 m CMOS process, using

parameters from table, VDD = 2.5V, and
minimum size NMOS ((W/L)n of 1.5)
VT0(V)

(V0.5)

VDSAT(V)

k(A/V2)

(V-1)

NMOS

0.43

0.4

0.63

115 x 10-6

0.06

PMOS

-0.4

-0.4

-1

-30 x 10-6

-0.1

=

## (W/L)p = 3.5 x 1.5 = 5.25 for a VM of 1.25V

EE415 VLSI Design

= 3.5

Simulated Inverter VM
VM is relatively insensitive to
variations in device ratio
setting the ratio to 3, 2.5
and 2 gives VMs of 1.22V,
1.18V, and 1.13V

VM (V)

## Increasing the width of the

PMOS moves VM towards VDD

~3.4

.1

(W/L)p/(W/L)n
Note: x-axis is semilog
EE415 VLSI Design

Noise Margins
Determining VIH and VIL
3

## By definition, VIH and VIL are where

dVout/dVin = -1 (= gain)

VOH = VDD

Vout

2
VM

VOL = GND 0

VIL

Vin VIH
A piece-wise linear
approximation of VTC
EE415 VLSI Design

## NMH = VDD - VIH

NML = VIL - GND
Approximating:
VIH = VM - VM /g
VIL = VM + (VDD - VM )/g
So high gain in the transition
region is very desirable

Vout (V)

## CMOS Inverter VTC from

Simulation
0.25um, (W/L)p/(W/L)n = 3.4
(W/L)n = 1.5 (min size)
VDD = 2.5V

2.5
2
1.5
1
0.5
0

VM 1.25V, g = -27.5
VIL = 1.2V, VIH = 1.3V
NML = NMH = 1.2

0.5

1
Vin (V)

1.5

2.5

## (actual values are

VIL = 1.03V, VIH = 1.45V
NML = 1.03V & NMH = 1.05V)

Output resistance
low-output = 2.4k
high-output = 3.3k

Gain Determinates
Vin
0

0.5

0
-2
-4

gain

-6

1.5

## Gain is a function of the current slope

in the saturation region, for Vin = VM
(1+r)
g ---------------------------------(VM-VTn-VDSATn/2)(n - p )

-8
-10
-12
-14
-16
-18

## EE415 VLSI Design

Determined by technology
parameters, especially .
Only designer influence through
supply voltage and VM (transistor
sizing).

Vout (V)

Variation
2.5
2
1.5
1 Good NMOS
0.5
0
0 0.5 1

Good PMOS
Nominal

Vin (V)

1.5

2.5

## Pprocess variations (mostly) cause a shift in the switching

threshold
EE415 VLSI Design

Vout (V)

Vout (V)

## Scaling the Supply Voltage

Gain=-1

Vin (V)
Device threshold voltages are
kept (virtually) constant

## EE415 VLSI Design

Vin (V)
Device threshold voltages are
kept (virtually) constant

Propagation
Delay

## Switch Model of Dynamic

Behavior
VDD

VDD

Rp
Vout

Vout
CL

Rn

CL

Vin = V DD
Vin = 0
Gate response time is determined by the time to charge C L
through Rp (discharge CL through Rn)
EE415 VLSI Design

VDD

VDD
M2
Vin

Cg4

Cdb2

Cgd12

M4

Vout

M1

Cdb1

Cw

Vout2

Cg3

M3

Interconnect

Fanout
Simplified
Model

## EE415 VLSI Design

Vin

Vout
CL

Delay
Approach 1
VDD

tpHL = CL Vswing/2
Iav
Vout

Iav

Vin = V DD
EE415 VLSI Design

CL

CL
kn VDD

## CMOS Inverter Propagation

Delay
Approach 2
VDD

tpHL = f(Ron.CL)
= 0.69 RonCL
Vout
CL
Ron

ln(0.5)

Vout
1

VDD

Vout VOH e

t /( Ron C L )

0.5
0.36

Vin = V DD
RonCL
EE415 VLSI Design

## CMOS Inverter: Transient Response

How can the designer build a fast gate?
tpHL = f(Ron*CL)
Keep output capacitance, CL, small
low fan-out
keep interconnections short (floor-plan
Decrease on-resistance of transistor
increase W/L ratio
make good contacts (slight effect)
EE415 VLSI Design

G

+
vgs

gmvgs

Define

ro

## VIH and VIL are based on derivative of VTC equal

to -1
EE415 VLSI Design

Transient Response

3
2.5

tp = 0.69 CL
(Reqn+Reqp)/2

2
Vout(V)

tpLH

tpHL

1.5
1

0.5
0
-0.5
0

0.5

## EE415 VLSI Design

t (sec)

1.5

2.5

-10

x 10

Inverter Transient
Response
3

VDD=2.5V
0.25m
W/Ln = 1.5
W/Lp = 4.5
Reqn= 13 k ( 1.5)
Reqp= 31 k ( 4.5)

Vin

2.5
2

Vout (V)

1.5

tpHL

tf

tpLH

tr

0.5

tpHL = 36 psec

tpLH = 29 psec

-0.5
0

0.5

1.5

t (sec)

2.5

x 10-10

## From simulation: tpHL = 39.9 psec and

EE415 VLSI Design

so
tp = 32.5 psec

5.5
5

tp(normalized)

4.5
4
3.5
3
2.5
2
1.5
1
0.8

1.2

1.4

1.6

VDD(V)

1.8

2.2

2.4

x 10-11

3.8

3.6

## The majority of improvement is

obtained for S = 5.

3.4
3.2

## Sizing factors larger than 10

barely yields any extra gain
(and cost significantly more
area).

tp(sec)

3
2.8
2.6
2.4
2.2
2
1

S
EE415 VLSI Design

11

13

15

(intrinsic capacitance
dominates)

x 10-11

tpLH

tpHL

tp(sec)

tp

= (W/Lp)/(W/Ln)

## EE415 VLSI Design

of 2.4 (= 31 k/13 k)
gives symmetrical
response
of 1.6 to 1.9 gives
optimal performance

## The input signal changes gradually

(and both PMOS and NMOS
conduct for a brief time).
This affects the current available for
charging/discharging CL and
impacts propagation delay.

## tp increases linearly with increasing

input rise time, tr, once tr > tp

## tr is due to the limited driving

capability of the preceding gate
EE415 VLSI Design

tp(sec)

x 10-11

ts(sec)
for a minimum-size inverter
with a fan-out of a single gate

x 10-11

Inverter
Sizing

## CMOS Inverter Sizing

Out
metal1
metal2
pdiff
metal1-diff via

In
metal1-poly via
polysilicon
VDD
PMOS (4/.24 = 16/1)
NMOS (2/.24 = 8/1)
ndiff

GND

## EE415 VLSI Design

metal2-metal1 via

Inverter Delay
Minimum length devices, L=0.25m
Assume that for WP = 2WN =2W
same pull-up and pull-down currents
approx. equal resistances RN = RP
approx. equal rise tpLH and fall tpHL delays
Analyze as an RC network
1
1
WP
WN

RP Runit
Runit
RN RW
Wunit
Wunit
Delay (D): tpHL = (ln 2) RNCL
EE415 VLSI Design

## tpLH = (ln 2) RPCL

C gin

W
3
Cunit
Wunit

2W

Delay

RW

CL
RW

tp = k RWCL
k is a constant, equal to 0.69
Assumptions: no load -> zero delay
EE415 VLSI Design

Wunit = 1

CP = 2Cunit

Delay

2W
W

Cint

CL

CN = Cunit
Delay = kRW(Cint + CL) = kRW Cint(1+ CL /Cint)
= Delay (Internal) + Delay (Load)
EE415 VLSI Design

Delay Formula
t p kR W C int 1 C L / C int t p 0 1 f /
Cint = Cgin

with 1

f = CL/Cgin

effective fanout

R = Runit/W ;
tp0 = 0.69RunitCunit
EE415 VLSI Design

Cint =WCunit

Inverter Chain

In

Out
Cg,1

## the delay of the j-th inverter stage is

tp,j = tp0 (1 + Cg,j+1/(Cg,j)) = tp0(1 + fj/ )

and

so

## tp = tp,j = tp0 (1 + Cg,j+1/(Cg,j))

If CL is given
How should the inverters be sized?
How many stages are needed to minimize the delay?

CL

## Optimum Delay and

Number of Stages
When each stage is sized by f and has same fanout f:

F C L / C gin ,1

## Effective fanout of each stage:

f NF
Minimum path delay

t p Nt p 0 1 N F /
EE415 VLSI Design

Example
In
C1

Out
1

f2

CL= 8 C1

## CL/C1 has to be evenly distributed across N = 3 stages:

f 38 2

t p 3t p 0 1 2 /

Notice that in this case we may not have any time savings
EE415 VLSI Design

Optimal Number of
Inverters

## What is the optimal value for N given F (=f N) ?

if the number of stages is too large, the intrinsic delay
dominates
if the number of stages is too small, the effective fan-out
dominates

## The optimum N is found by differentiating the minimum

delay divided by the number of stages and setting the
result to 0,
effective-fan out becomes f = e = 2.71828
EE415 VLSI Design

Optimum Number of
Stages
For a given load, CL and given input capacitance Cin
Find optimal sizing f
ln F
N
C L F Cin f Cin with N
ln f

t p Nt p 0 F

1/ N

/ 1

t p 0 ln F

t p t p 0 ln F ln f 1

ln 2 f

For = 0, f = e, N = lnF
EE415 VLSI Design

ln f ln f
f
0

f exp1 f

normalized delay

Fop

## Choosing f larger than optimum has little effect on delay and

reduces the number of stages (and area).
Common practice to use f = 4 (for = 1)
Too many stages has a negative impact on delay

## EE415 VLSI Design

Example of Inverter
(Buffer) Staging
1
Cg,1 = 1

CL = 64 Cg,1
8

1
Cg,1 = 1

tp

64

65

18

15

2.8

15.3

16

Cg,1 = 1
1

CL = 64 Cg,1
4

2.8

Cg,1 = 1
EE415 VLSI Design

CL = 64 Cg,1
8

22.6
CL = 64 Cg,1

for Large CL

F ( = 1)

Unbuffered

Two Stage
Chain

Opt. Inverter
Chain

10

11

8.3

8.3

100

101

22

16.5

1,000

1001

65

24.8

10,000

10,001

202

33.1

## Impressive speed-ups with optimized cascaded inverter

chain for very large capacitive loads.

Design Challenge

## Keep signal rise times < gate propagation delays.

good for performance
good for power consumption

## Keeping rise and fall times of the signals of

approximately equal values is one of the major
challenges in - slope engineering.

Power
Dissipation

## EE415 VLSI Design

Power Dissipation
Power consumption determines heat dissipation and
energy consumption
Power influences design decisions:
packaging and cooling
width of supply lines
power-supply capacity
# of transistors integrated on a single chip
Power requirements make high density bipolar ICs
impossible (feasibility, cost, reliability)
EE415 VLSI Design

Power Dissipation
Supplyline sizing

Battery
drain,
cooling

## EE415 VLSI Design

Power Dissipation
Ppeak = static power + dynamic power
Dynamic power:
(dis)charging capacitors
temporary paths from VDD to VSS
proportional to switching frequency
Static power:
static conductive paths between rails
leakage
increases with temperature
EE415 VLSI Design

Power Dissipation
Propagation delay is related to power
consumption
tp determined by speed of charge transfer
fast charge transfer => fast gate
fast gate => more power consumption
Power-delay product (PDP)
quality measure for switching device
PDP = energy consumed /gate / switching
event
measured using ring oscillator
EE415 VLSI Design

Power Dissipation
Supplyline sizing

Battery
drain,
cooling

## Energy consumed /gate

/switching event

Response
CMOS technology:
No path exists between VDD and VSS in
No static power consumption! (ideally)
Main reason why CMOS replaced NMOS
NMOS technology:
Has NMOS pull-up device that is always ON
Creates voltage divider when pull-down is
ON
Power consumption limits # devices / chip
EE415 VLSI Design

Dynamic Power
Dissipation
Vdd

Vin

Vout
CL

Energy/transition = CL * Vdd2
Power = Energy/transition * f = CL * Vdd2 * f

## Not a function of transistor sizes!

Need to reduce CL, Vdd, and f to reduce power.
EE415 VLSI Design

## Modification for Circuits with Reduced Swing

Vdd
Vdd
VddVt
CL

E 0 1 = CL Vdd V dd Vt

## Can exploit reduced swing to lower power

(e.g., reduced bit-line swing in memory)
EE415 VLSI Design

## Node Transition Activity and Power

Consider switching a CMOS gate for N clock cycles
E

= C V 2 n N
N
L
dd

## EN : the energy consumed for N clock cycles

n(N): the number of 0->1 transition in N clock cycles
EN
2
n N
P avg = lim fclk = lim C Vdd f clk
N N
N N
L

## EE415 VLSI Design

01

n N
lim
N N

P av g = 0 1 C Vdd 2 f clk
L

Vdd

Vin

Vout
CL

IVDD (mA)

0.15

0.10

0.05

0.0

1.0

2.0
3.0
Vin (V)

4.0

5.0

## Short circuit current goes to zero if tout_fall >> tin_rise,

but cant do this for cascade logic.

8
7

Vdd =3.3

Vdd =2.5

Pnorm

5
4
3

Vdd =1.5

2
1
0

tsin/tsout

## Keep the input and output rise/fall times equal

If VDD<Vth+|Vtp| then short circuit power can be eliminated
EE415 VLSI Design

Leakage
Vdd

Vout

Drain Junction
Leakage
Sub-Threshold
Current

## Sub-threshold currents rise exponentially

Sub-Threshold Current Dominant Factor
with temperature.
EE415 VLSI Design

## Reverse-Biased Diode Leakage

GATE

p+

p+

ReverseLeakageCurrent
+

V
dd

IDL=JSA

## JS = 10-100 pA/mm2 at 25 deg C for 0.25mm CMOS

2
fora1.2mCMOStechnology
JS =15pA/m
JS doubles
for every
9 deg C!
J doublewithevery9oCincreaseintemperature

s

Vdd

Istat

Vin =5V

Vout

CL

## Pstat = P(In=1).Vdd . Istat

Dominates over dynamic consumption
EE415 VLSI Design

Reduction

## Prime choice: Reduce voltage!

Supply voltage was reduced from 5 V to 1V over
the years
25 time reduction of switching power

## Reduce switching activity

Reduce physical capacitance
Device Sizing: for F=20
fopt(energy)=3.53, fopt(performance)=4.47

## Voltage scaling has

stopped as well
kT/q does not scale
Vth scaling has power
consequences

## If Vdd does not scale

Energy scales slowly
EE415 VLSI Design

Ed Nowak, IBM

Impact of
Technology
Scaling

## EE415 VLSI Design

Goals of Technology
Scaling

## Make things cheaper:

Want to sell more functions (transistors)
per chip for the same money
Build same products cheaper, sell the
same part for less money
Price of a transistor has to be reduced

lower power

## EE415 VLSI Design

Technology Scaling

## Goals of scaling the dimensions by 30%:

Reduce gate delay by 30% (increase operating
frequency by 43%)
Double transistor density
Reduce energy per transition by 65% (50% power
savings @ 43% increase in frequency

## Die size used to increase by 14% per

generation
Technology generation spans 2-3 years

Technology Nodes
Green
in use
Orange
- in development
Blue
in plans

## Minimum Feature Size

(nm)

Technology Nodes
350
180
100
50
25
13

EE415 VLSI Design

## Technology Nodes and

Minimum Feature Sizes
35
0
25
0
18
0
13
0
90
65
45
32
EE415 VLSI Design

Leakage currents

Currents [A/m]

Supply voltage

## EE415 VLSI Design

Acceleration Continues

## EE415 VLSI Design

Acceleration Continues
SAT TV/WLAN
IMT2000

## UWC136 Satellite Comm.

LMDS

Automotive Military

76...78 94

201
6
201
3
201
0
200
7

200
4
EE415 VLSI Design
200
CMOS

SiGe-BICMOS

III-V (InP)

Technology Scaling

10

10

10

10

-1

-2

10
1960

1970

1980

1990

Year

2000

## Minimum Feature Size

2010

Technology Scaling
tp decreases by
13%/year
50% every
5 years!

## EE415 VLSI Design

Propagation Delay

## Technology Scaling Models

Full Scaling (Constant Electrical Field)
ideal model dimensions and voltage scale
together by the same factor S

## Fixed Voltage Scaling

most common model until recently
only dimensions scale, voltages remain constant

General Scaling
most realistic for todays situation
voltages and dimensions scale with different factors
EE415 VLSI Design

Devices

## EE415 VLSI Design

Transistor Scaling
(velocity-saturated devices)

Dilbert