ACPD Presentation at

SiliconWorks(Automated Custom Physical

Design)
Cadence Korea
May.13.2003

SY.Lee

CADENCE CONFIDENTIAL

Agenda
What is ACPD?
Virtuoso-XL
VCP
VCR
PDK
RoadMap

CADENCE CONFIDENTIAL

What is ACPD ?
Automated Custom Physical Design
Complete automated full custom layout methodology for digital,
analog and mixed technologies at all levels of the design
hierarchy
No compromises: Layout results are equal to manual full custom
Low risk: Customer proven solution in use worldwide
Provides a measurable and consistent productivity increase of
4X - 10X on average compared to current methods

ACPD
Tools

Methodology

CADENCE CONFIDENTIAL

Manual Physical Design Layout

Methodology
Virtuoso Schematic
Composer
Physical Handoff

CMOS Process
Library with
Pcells.

Virtuoso Layout Editor

with Pcells

Diva DRC,LVS

No connectivity

No constraints or
automated routing

Many DRC/LVS loops

to fix errors

Total time for Block Creation: typically 7 days

Total time for Chip Assembly: typically 6 weeks
CADENCE CONFIDENTIAL

ACPD Methodology
Netlist

CMOS Process
Library with
Pcells.

Virtuoso Schematic
Composer
Virtuoso XL (VXL)
and
ROD Pcells

Virtuoso Custom
Placer (VCP)

Process Design Kits

(PDKs)

Virtuoso Custom Router

(VCR)
/Cadence Chip Assembly
Router (CCAR)

DIVA DRC/LVS

Introduced in 1999
Connectivity
Driven Layout
Constraint and
Connectivity Based
Editing
Automated Device
Placement
Constraint
Driven Correct-byConstruction
Routing
Number of DRC/LVS
Errors Significantly
Reduced

Total time for Block Creation now - 1 day Vs 7 DAYS (7X)

Total time for Chip Assembly now - 1 day Vs 6 WEEKS (30X)
CADENCE CONFIDENTIAL

ACPD: METHODOLOGY AND

PRODUCTS

Connectivity & constraints

Generatio
n

Placement
Place

Routin
g

Verification

Virtuoso
Virtuoso Schematic
Schematic Composer
Composer

Virtuoso
Virtuoso XL
XL Layout
Layout Editor
Editor
Custom
Custom Placement
Placement
Interactive
Interactive Routing
Routing

Assura
Assura /Diva
/Diva (DRC/LVS)
(DRC/LVS)

= DAYS

= MONTHS

Provides consistent 100% LVS &

DRC correct results using
Connectivity & Constraints
Generates faster more accurate
devices using advanced interactive
editing techniques
Reduces the layout time
dramatically with automated
placement and interactive routing
Maximizes custom layout
productivity to deliver handcrafted
quality in a fraction of the time

Generation

CADENCE CONFIDENTIAL

Virtuoso-XL
Virtuoso-XL Layout Editor is the next-generation, connectivity- and
constraint-driven layout design environment. A task-oriented design
approach provides direct access to automated placement, routing,
verification and a robust set of interactive layout editing utilities. This new
physical design solution maximizes custom layout productivity to deliver
handcrafted quality layout in a fraction of the time of traditional
methodologies
Provides a unified and consistent layout editing environment
Includes full-function polygon editing for high-performance, handcrafted IC layout
Automatically chains and folds transistors
Provides fast cell-level layout
Ensures increased productivity and correct-by-construction results
Provides fast device manipulation with stretchable parameterized cells (Pcells)

CADENCE CONFIDENTIAL

Rows displayed for preplacement

DEVICE GENERATION
Pins generated from template

Pcells generated from netlist or schematic parameters

Connectivity driven - Netlist-Driven

Alternate independent
connectivity sources:

Vsc

VXL

schematic
netlist

Similar use modes and

capabilities
Imported netlists
managed by DM

Edit, Place, Route...

Netlist
* SPICE
*
M01 2 3 gnd 27 W=2 L=3
M02 3 5 g1 15 W=2u L=4u
M03 4 5 g2 216 W=1u L=1u
M04 5 6 g3 11 W=3u L=1.2u
M05 5 6 g4 12 W=3u L=1u
M12 3 5 g1 15 W=2u L=4u
M13 4 5 g6 26 W=1u L=1u
M14 5 6 g7 11 W=3u L=1.2u
M15 5 6 g8 12 W=3u L=1u
...

CADENCE CONFIDENTIAL

Layout editing - Automatic Abutment

DRC correct

(2) metal pins touch

and trigger abutment

Constraint correct
A B

Technology independent
Backward compatible

(1) B is moved
to overlap A

Customizable
Interactive

(3) A and B are

transformed and
snap to min dist.

Post-processor after
placement
(4) When A is moved away,
reverse transformations
occur to both instances

CADENCE CONFIDENTIAL

Connectivity driven - Pick from

Schematic
CBE link

Schematic reference

Constraint-driven
interactive placement

Multiple simultaneous
selections

Pre-placement as in
schematic

Virtuoso XL

Composer

Edit Place Route ...

(3)
(1)

(1) Select unplaced

component from
schematic

(2)

(2) Drag mouse

pointer into
layout window

(3) Interactively
place newly
created object

CADENCE CONFIDENTIAL

Interactive Chaining & Folding (contd)

CADENCE CONFIDENTIAL

Stretchable pCells

CADENCE CONFIDENTIAL

Virtuoso custom placer (Vcp) - Overview

Available in 4.4.6 3Q 2000
Automatic and interactive support in Virtuoso XL
Constraint-driven (physical placement constraints)
Row-based placement:
Transistor Devices
Custom and Std. Cells
Blocks

Area-based placement
Mixed mode placement
CADENCE CONFIDENTIAL

Standard Cells

PLACEMENT
RESULTS
Filler Cells

Filler Cells

WE

Show Timing/Length
Constraints: Displays
length rule indicators as
with a length rule is

Meter displays a negative number in

green color if within the length rule limits.
positive number in Red color shows up
path being created is outside
Octagon shows the extent to which a path
be routed within the length rules.

Rule
a path
edited.
A
when the
length limits.
can

CADENCE CONFIDENTIAL

Virtuoso Custom Router

Original and most proven IC shape-based area routing technology in the
industry
Provides connectivity- and constraint-driven interactive and automatic
routing with online DRC/LVS checking
Comprehensive set of routing constraints with hierarchical rule
precedence

Wire to Wire

Wire to
Via

Wire Shape

Wire to Keepout

Automated interactive bus routing

Path Search

Automated interactive and automatic power routing

Via to Pin

Wire to
Pin

Supports cross-probing and dynamic updating between schematic and

layout

CADENCE CONFIDENTIAL

CADENCE CONFIDENTIAL

VCD
VCD Solution
Solution
Point Tools VCD Solution

ACPD Methodology

PDK (a)

PDK (b)

User 1

99 year or TBL
User 1

Virtuoso

User 2

VCD

ools
T
f
lo
Po o
VXL
VXL
VCR/CCAR
VCR/CCAR
DIVA
DIVA

Virtuoso
User 3
VXL
Introduced in 1999

Virtuoso
Virtuoso
VXL
VXL
VCR &
VCR &
Proute
Proute
DIVA &
DIVA &
Assura
Assura
VCP
VCP
Methodology
Methodology
Installation
Installation
Internet
Internet
Training
Training

TBL only
VCD Seat

User 2

VCD Seat

User 3

VCD Seat

Q1 2001
CADENCE CONFIDENTIAL

What is a baseline foundry PDK?

For example CMOS logic
Composer logic symbol library
N & P mos, resistor and capacitor Pcells
Virtuoso XL/VCP/VCR Tech and display files
Assura/Diva DRC/LVS decks (download from foundry site)

Foundries
e.g. TSMC., UMC etc..

Technologies
e.g. .18u, .25u, Logic.., MS., RF etc..

Tested with VCD methodology

Supported (maintenance available)
Price book orderable item

CADENCE CONFIDENTIAL

PDK
Tool Support
Foundry

Build
PDK

Schematic Symbols

Virtuoso Schematic
Composer

Simulation
Simulation Models
Models

Spectre, Spectre RF

Technology File

Virtuoso XL
Custom Placer
Custom
Router

Parameterized cells
( Pcells)

Virtuoso XL

Verification
Verification Decks
Rule decks

DIVA & Assura

DRC/LVS

PDK
Components

Process data

Per FAB / Process

e.g. TSMC .18 CMOS
(proprietary data)

Foundry

CADENCE CONFIDENTIAL

Cadence IC Design Environment

OpenAccess

Leverages industry
knowledge on one
standard

5.0 supports
OpenAccess in Q1 03

Cell-Based AMS/Custom

SOC
Encounter

Custom IC
Design

Industry-Standard
open-source model

3rd Party
Tool
3rd Party
Tool
3rd Party
Tool

Improved tool and flow

interoperability

Standards Accelerate Technology Development

And Reduce Costs
CADENCE CONFIDENTIAL

LINUX OS Support
IC Solutions
Provide Enterprise
class solutions through
partnerships with HP,
IBM and RedHat

Custom IC solution
available 1Q03

Many digital solutions

available now remainder 4Q02

Physical verification
rollout 3Q02 through
3Q03

CADENCE CONFIDENTIAL

CADENCE CONFIDENTIAL