The 8051 Microcontroller and Embedded Systems: 8051 Addressing Modes

The 8051 Microcontroller and
Embedded Systems
CHAPTER 5
8051 ADDRESSING
MODES
OBJECTIVES
List the five addressing modes of the 8051 microcontroller

Contrast and compare the addressing modes
Code 8051 Assemblv language instructions using each
addressing mode
Access RAM using various addressing modes
List the SFR (special function registers) addresses
Discuss how to access the SFR
Manipulate the stack using direct addressing mode
Code 8051 instructions to manipulate a look-up table
Access RAM, I/O, and ports using bit addresses
Discuss how to access the extra 128 bytes of RAM space in
the 8052
Addressing Modes
The various addressing modes of a

microprocessor are determined when it is
designed, and therefore cannot be changed by
the programmer.
The 8051 provides a total of five distinct
addressing modes.
(1) immediate
(2) register
(3) direct
(4) register indirect
(5) indexed
Immediate addressing mode

The
operand comes immediately after the

op-code.
The immediate data must be preceded by
the pound sign, "#".
Register addressing mode

Register
addressing mode involves the

use of registers to hold the data to be
manipulated.
SECTION 5.2: ACCESSING MEMORY

USING VARIOUS ADDRESSING MODES
Direct addressing mode

There are 128 bytes of RAM in the 8051.
The RAM has been assigned addresses 00 to
7FH.
1. RAM locations 00 - 1 FH are assigned to the register

banks and stack.
2. RAM locations 20 - 2FH are set aside as bitaddressable space to save singlebit data.
3. RAM locations 30 - 7FH are available as a place to
save byte-sized data.

It
is most often used to access RAM

locations 30 - 7FH.
This is due to the fact that register bank
locations are accessed by the register names
of R0 - R7.
There is no such name for other RAM
locations so must use direct addressing.

In
the direct addressing mode, the data is in

a RAM memory location whose address is
known, and this address is given as a part of
the instruction.
Special Function Registers

In
the 8051, registers A, B, PSW, and DPTR

are part of the group of registers commonly
referred to as SFR.
The SFR can be accessed by their names or
by their addresses.
For example, register A has address E0H
and register B has been designated the
address F0H.
SFR
SECTION 5.2: ACCESSING MEMORY

USING VARIOUS ADDRESSING MODES
SFR
registers and their addresses
Table 51
8051 Special Function Register
(SFR) Addresses
Stack and direct addressing mode
Another major use of direct addressing mode is

the stack.
In the 8051 family, only direct addressing mode
is allowed for pushing onto the stack.
An instruction such as "PUSH A" is invalid.
Pushing the accumulator onto the stack must be
coded as "PUSH 0E0H.
Direct addressing mode must be used for the
POP instruction as well.
"POP 04" will pop the top of the stack into R4 of
bank 0.
Register indirect addressing mode
A register is used as a pointer to the data.

If the data is inside the CPU, only registers R0
and R 1 are used for this purpose.
R2 - R7 cannot be used to hold the address of an
operand located in RAM when using indirect
addressing mode.
When RO and R 1 are used as pointers they must
be preceded by the @ sign.
Register indirect addressing mode
Advantage of register indirect addressing

mode
One
of the advantages of register indirect

addressing mode is that it makes
accessing data dynamic rather than static
as in the case of direct addressing mode.
Looping is not possible in direct
addressing mode.
This is the main difference between the
direct and register indirect addressing
modes.
Advantage of register indirect addressing

mode
Limitation of register indirect addressing

mode in the 8051
R0 and R 1 are the only registers that can be

used for pointers in register indirect addressing
mode.
Since R0 and R l are 8 bits wide, their use is
limited to accessing any information in the
internal RAM (scratch pad memory of 30H - 7FH,
or SFR).
To access data stored in external RAM or in the
code space of on-chip ROM, we need a 16-bit
pointer, the DPTR.
Indexed addressing mode and onchip ROM access
Indexed addressing mode is widely used in accessing data

elements of look-up table entries located in the program
ROM space of the 8051.
The instruction used for this purpose is :
MOVC A, @ A+DPTR
The 16-bit register DPTR and register A are used to form

the address of the data element stored in on-chip ROM.
Because the data elements are stored in the program
(code) space ROM of the 8051, the instruction MOVC is
used instead of MOV. The "C" means code.
In this instruction the contents of A are added to the 16-bit
register DPTR to form the 16bit address of the needed
data.
Indexed addressing mode and MOVX

instruction
The 8051 has another 64K bytes of memory space set

aside exclusively for data storage.
This data memory space is referred to as external memory
and it is accessed by the MOVX instruction.
The 8051 has a total of 128K bytes of memory space since
64K bytes of code added to 64K bytes of data space gives
us 128K bytes.
One major difference between the code space and data
space is that, unlike code space, the data space cannot be
shared between code and data.
SECTION 5.3: BIT ADDRESSES FOR

I/O AND RAM
Many microprocessors such as the 386 or Pentium allow

programs to access registers and I/0 ports in byte size only.
If you need to check a single bit of an I/0 port, you must read
the entire byte first and then manipulate the whole byte with
some logic instructions to get hold of the desired single bit.
This is not the case with the 8051.
One of the most important features of the 8051 is the ability to
access the registers, RAM, and I/0 ports in bits instead of
bytes.
This is a very unique and powerful feature for a microprocessor
made in the early 1980s.

I/O AND RAM
Bit-addressable
RAM
Figure 51
16 Bytes of Internal RAM. Note:
They are both bit- and byte-accessible.

I/O AND RAM
Bit-addressable
Table 52
RAM
Single-Bit Instructions

I/O AND RAM
I/O
port bit addresses
Figure 52
SFR RAM Address (Byte and Bit)

I/O AND RAM
Bit
memory map
Table 53
Bit Addresses for All Ports

I/O AND RAM
Registers
bit-addressability
Figure 53
Bits of the PSW Register
Types Of Instructions
1.
2.
3.
4.
5.
Data transfer instructions.

Arithmetic instructions.
Logical instructions.
Logical instructions with bits.
Branch instructions.
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Data Transfer Instructions

These
instructions move the content of one

register to another one.
Data
can be transferred to stack with the help

of PUSH and POP instructions.

MNEMONIC
DESCRIPTION
BYTES
MOV
A,Rn
(A)
(Rn)
MOV
A,Rx
(A)
(Rx)
MOV
A,@Ri
(A)
(Ri)
1

MOV
A,#X
(A)
Data
MOV
Rn,A
(Rn)
(A)
MOV
Rn, Rx
(Rn)
(Rx)

MOV
Rn, #X
(Rn)
Data
MOV
Rx, A
(Rx)
(A)
MOV
Rx, Rn
(Rx)
(Rn)

MOV
Rx, Ry
(RX)
(Ry)
MOV
Rx, @ Ri
(Rx)
(Ri)
MOV
Rx, # X
(Rx)
Data

MOV
@ Ri, A
(Ri)
(A)
MOV
@ Ri, Rx
(Ri)
(Rx)
MOV
@ Ri, #X
(Ri)
Data

MOV
DPTR, #X
MOVC
A@
A+DPTR
MOVC
A@
(DPTR)
Data
(A)
(A+DPTR)
(A)
(A+PC)
A+PC
MOVX
A,@ Ri
MOVX
A, @
(A)
@Ri, A
(Ri)
(Ri)
(DPTR)
DPTR
MOVX
(A)
1

MOVX
@
DPTR, A
(DPTR)
PUSH
POP
(A)
Rx
Push directly
addressed Rx register on stack
Rx
(A)
(Rx)

XCH
A, Rn
(A)
(Rn)
XCH
A, Rx
(A)
(Rx)
XCH
A, @Ri
(A)
(Ri)

XCHD
Exchange 4 lower
1
bits in accumulator with indirectly
addressed register
Arithmetic Instructions
These
instructions perform several basic

operations. After execution, the result is
stored in the first operand.
bit addition, subtraction, multiplication,

increment-decrement instructions can be
performed.
MNEMONICS
DESCRIPTION
BYTE
ADD
A, Rn
A = A + Rn
ADD
A, Rx
A = A + Rx
AAD
A, @ Ri
A = A+ Ri
1
ADD
A, # X
A = A + Byte
ADDC
A, Rn
A = A + Rn + C
ADDC
A , Rx
A = A + Rx + C
ADDC
A, @ Ri
A = A + Ri + C
ADDC
A, # X
A = A + Byte + C
SUBB
A, Rn
A = A Rn 1
SUBB
A, Rx
A = A Rx 1
SUBB
A, @ Ri
A = A Ri 1
SUBB
A, # X
A = A Byte 1
INC
A= A+ 1
INC
Rn
Rn = Rn + 1
INC
Rx
Rx = Rx + 1
INC
@ Ri
Ri = Ri + 1
DEC
A= A 1
DEC
Rn
Rn = Rn 1
DEC
Rx
Rx = Rx 1
DEC
@ Ri
Ri = Ri 1
DPTR = DPTR + 1
INC
DPTR
MUL AB
B:A = A * B
DIV
A = [A/B]
AB
DA A
Decimal adjustment of
1
accumulator according to BCD code
Logical Instructions
These
instructions perform logical operations

between two register contents on bit by bit
basis.
After
execution, the result is stored in the first

operand.
MNEMONIC
DESCRIPTION
ANL A,
Rn
(A)
(A) ^ (Rn)
ANL A,
Rx
(A)
(A) ^ (Rx)
(A)
(A) ^ (Ri)
ANL A,@
Ri
BYTE
ANL A,
#X
(A) (8 bit data) ^ (A)
ANL
Rx, A
(Rx)
(A) ^ (Rx)
ANL
Rx,# X
(Rx) (8 bit data) ^ (Rx)
2
2
3
ORL A,
Rn
(A)
(A) + (Rn)
ORL A,
Rx
(A)
(A) + (Rx)
ORL A,
@ Ri
(A)
(A) + (Ri)
ORL
Rx, A
(Rx) (A) + (Rx)
ORL
Rx,# X
(Rx) (8 bit data) + (Rx)
XORL A,
Rn
Logical exclusive
OR operation between the contents of
accumulator and R register.
XORL A,
Rx
Logical exclusive OR
2
operation between the contents of the
accumulator and directly addressed register
Rx.
XORL A,@ Ri
1
operation between the
contents of the accumulator and directly
addressed register.
XORL A,
#X
2
operation between the contents of
accumulator and the given 8 bit data.
XORL Rx, A
2
accumulator and directly addressed register
Rx.
XORL
Rx, # X
Logical exclusive OR 3
directly addressed register Rx and the given
8 bit data.
CLR A
(A) 0
1
CPL A
(A)
(/A)
1
SWAP
RL A
RLC
(A3-0)
(A7-4)
(An + 1)
(A0)
(An + 1)
(A0)
(C)
(An)
(A7)
(An)
(C)
(A7)
1
1
RR
RRC
(An)
(A7)
(An + 1)
(A0)
(An)
(A7)
(C)
(An + 1)
(C)
(A0)
Logical Instructions On Bits

Similar
to logical instructions, these

instructions also perform logical operations.
The
difference is that these operations are

performed on single bits.

MNEMONIC
CLR
CLR
bit
SETB
DESCRIPTION
(C=0)
BYTE
1
clear directly addressed bit 2

(C=1)
1

SETB
bit
Set directly
2
addressed bit
CPL
(1 = 0, 0 = 1)
CPL
bit
Complement directly
addressed bit
1
2

ANL
C, bit
Logical AND operation 2
between Carry bit and directly addressed
bit.
ANL
C,/bit
Logical AND operation
between Carry bit and inverted directly
addressed bit.

ORL
C, bit
Logical OR operation
2
between Carry bit and directly addressed
bit.
ORL
C,/bit
Logical OR operation
between Carry bit and inverted directly
addressed bit.

MOV
C, bit
Move directly addressed 2
bit to carry bit.
MOV
bit, C
Move Carry bit to directly 2
addressed bit.
Program Flow Control Instructions

In
this group, instructions are related to the

flow of the program, these are used to
control the operation like, JUMP and CALL
instructions.
Some
instructions are used to introduce

delay in the program, to the halt program.

MNEMONIC
ACALL
adr11
DESCRIPTION
(PC)
(SP)
((SP))
(SP)
((SP))
(PC) + 2
(SP) + 1
(PC7 0)
(SP) + 1
(PC15-8)
BYTE
2

LCALL
adr16
(PC)
(SP)
((SP))
(SP)
((SP))
(PC)
(PC) + 3
(SP) + 1
(PC7-0)
(SP) + 1
(PC15-8)
addr15-0

RET
(PC15-8)
(SP)
(PC7-0)
(SP)
((SP))
(SP) 1
((SP))
(SP) - 1

RET1
AJMP
addr11
(PC15-8)
(SP)
(PC7-0)
(SP)
((SP))
(SP) 1
((SP))
(SP) 1
(PC)
(PC10-0)
(PC) + 2
1
page address

LJMP
addr16
SJMP
rel
(PC)
addr15-0
short jump from

2
(from -128 to +127 locations in
relation to first next instruction)

JC
rel
JNC
rel
(PC)
(PC) + 2
IF ( C ) = 1
THEN (PC)
(PC) + rel
(PC) (PC) + 2
IF ( C) = 0
THEN (PC)
(PC) + rel

JB
bit, rel
Jump if addressed
bit is set. Short jump.

JBC
bit, rel
Jump if addressed
bit is set and clear it.
Short jump.

JMP
JZ
@A + DPTR (PC)
rel
(A) + (DPTR)
(PC) (PC) + 2
IF (A) = 0
THEN (PC) (PC) + rel
1
2

JNZ
rel
(PC)
(PC) + 2
IF (A) = 0
THEN (PC)
(PC) + rel
CJNE
A, Rx, rel
Compare the contents 3
of acc. And directly addressed register Rx.
Jump if they are different. Short jump.

CJNE
A, #X, rel
(PC)
(PC) + 3
3
IF ( A) < > data
THEN (PC)
(PC) + relative
offset
IF (A) < data
THEN ( C )
1
ELSE ( C )
0

CJNE
@ RI, # x, rel
(PC)
(PC) + 3
3
IF (Rn) <> data
THEN (PC)
(PC) + relative
offset
IF (Rn) < data
THEN ( C )
1
ELSE ( C )
0

CJNE
@ Ri, # X, rel (PC) (PC) + 3

3
IF ((Ri)) <> data
THEN (PC) (PC) + relative
offset
IF ((Ri)) < data
THEN ( C ) 1
ELSE ( C ) 0

DJNZ
Rn , rel
(PC) (PC) + 2
2
(Rn)
(Rn) - 1
IF (Rn) > 0 or (Rn) < 0
THEN (PC)
(PC) + rel

DJNZ
NOP
Rx, rel
(PC)
(Rx)
IF (Rx) >
THEN (PC)
(PC) + 2
3
(Rn) 1
0 or (Rx) < 0
(PC) + rel
No operation
Summary
Instruction
set.
Addressing modes.
Data transfer instruction.
Arithmetic instruction.
Logical instruction.
Logical operation on bits.
Using BIT directive

The
BIT directive is a widely used

directive to assign the bit-addressable I/0
and RAM locations.
The BIT directive allows a program to
assign the I/0 or RAM bit at the beginning
of the program, making it easier to modify
them.
Using EQU directive

We
can also use the EQU directive to

assign addresses.
Next
Lecture
Problems Textbook Chapter 5
Answer as many questions as you can and

submit via MeL before the end of the lecture.
Proteus
Exercise Textbook Chapter 5
Do as much of the Proteus exercise as you can

and submit via MeL before the end of the lecture.

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The 8051 Microcontroller and

List the five addressing modes of the 8051 microcontroller

The various addressing modes of a

Immediate addressing mode

operand comes immediately after the

Register addressing mode

addressing mode involves the

SECTION 5.2: ACCESSING MEMORY

Direct addressing mode

1. RAM locations 00 - 1 FH are assigned to the register

Direct addressing mode

is most often used to access RAM

Direct addressing mode

the direct addressing mode, the data is in

Special Function Registers

the 8051, registers A, B, PSW, and DPTR

SECTION 5.2: ACCESSING MEMORY

registers and their addresses

Stack and direct addressing mode

Another major use of direct addressing mode is

Register indirect addressing mode

A register is used as a pointer to the data.

Register indirect addressing mode

Advantage of register indirect addressing

of the advantages of register indirect

Advantage of register indirect addressing

Limitation of register indirect addressing

R0 and R 1 are the only registers that can be

Indexed addressing mode and onchip ROM access

Indexed addressing mode is widely used in accessing data

The 16-bit register DPTR and register A are used to form

Indexed addressing mode and MOVX

The 8051 has another 64K bytes of memory space set

SECTION 5.3: BIT ADDRESSES FOR

Many microprocessors such as the 386 or Pentium allow

SECTION 5.3: BIT ADDRESSES FOR

SECTION 5.3: BIT ADDRESSES FOR

SECTION 5.3: BIT ADDRESSES FOR

port bit addresses

SFR RAM Address (Byte and Bit)

SECTION 5.3: BIT ADDRESSES FOR

Bit Addresses for All Ports

SECTION 5.3: BIT ADDRESSES FOR

Bits of the PSW Register

Data transfer instructions.

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Data Transfer Instructions

instructions move the content of one

can be transferred to stack with the help

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Data Transfer Instructions

Data Transfer Instructions

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Data Transfer Instructions

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Data Transfer Instructions

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Data Transfer Instructions

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Data Transfer Instructions

Data Transfer Instructions

Data Transfer Instructions

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