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Reducing Misses
Classifying Misses: 3 Cs
CompulsoryThe first access to a block is not in the cache, so the
block must be brought into the cache. Also called cold start misses
or first reference misses.
(Misses in even an Infinite Cache)
CapacityIf the cache cannot contain all the blocks needed during
execution of a program, capacity misses will occur due to blocks
being discarded and later retrieved.
(Misses in Fully Associative Size X Cache)
ConflictIf block-placement strategy is set associative or direct
mapped, conflict misses (in addition to compulsory & capacity
misses) will occur because a block can be discarded and later
retrieved if too many blocks map to its set. Also called collision
misses or interference misses.
(Misses in N-way Associative, Size X Cache)
0.14
1-way
0.12
Conflict
2-way
0.1
4-way
0.08
8-way
0.06
Capacity
0.04
0.02
64
32
16
128
Note: Compulsory
Miss small
Compulsory
DAP Spr.98 UCB 5
0.12
Conflict
2-way
0.1
4-way
0.08
8-way
0.06
Capacity
0.04
0.02
128
64
32
16
0.14
Compulsory
DAP Spr.98 UCB 6
20%
15%
16K
10%
64K
5%
256K
256
128
64
32
0%
16
Miss
Rate
4K
Associativity
1-way 2-way
2.15
2.07
1.86
1.76
1.67
1.61
1.48
1.47
1.32
1.32
1.24
1.25
1.20
1.21
1.17
1.18
4-way
2.01
1.68
1.53
1.43
1.32
1.27
1.23
1.20
8-way
5. Reducing Misses by
Prefetching of Instructions & Data
Instruction prefetching Sequentially prefetch
instructions from IM to the instruction Queue (IQ)
together with branch prediction All computers
employ this.
Data prefetching Difficult to predict data that will
be used in future. Following questions must be
answered.
1. What to prefetch? How to know which data will
be used? Unnecessary prefetches will waste
memory/bus bandwidth and will replace useful
data in the cache (cache pollution problem) giving
rise to negative impact on the execution time.
2. When to prefetch? Must be early enough for
the data to be useful, but too early will cause
cache pollution problem.
DAP Spr.98 UCB 12
Data Prefetching
Software Prefetching Explicit instructions to
prefetch data are inserted in the program.
Difficult to decide where to put in the program.
Needs good compiler analysis. Some computers
already have prefetch intructions. Examples are:
-- Load data into register (HP PA-RISC loads)
Cache Prefetch: load into cache
(MIPS IV, PowerPC, SPARC v. 9)
Summary
CPUtime IC CPI
Execution
Memory accesses
Instruction
Miss PenaltyL2)
Definitions:
Local miss rate misses in this cache divided by the total number of
memory accesses to this cache (Miss rateL2)
Global miss ratemisses in this cache divided by the total number
of memory accesses generated by the CPU
(Miss RateL1 x Miss RateL2)
Global Miss Rate is what matters
CPUtime IC CPI
Execution
Memory accesses
Instruction
Five techniques
miss penalty
miss rate
MR
+
+
+
+
+
+
+
MP HT
+
+
+
+
+
Complexity
0
1
2
2
2
3
0
1
1
2
3
2