Semiconductor Industry

Thesemiconductor industryis the aggregate

collection of companies engaged in thedesign

andfabricationofsemiconductor devices. It
formed around 1960, once the fabrication of
semiconductors became a viable business. It
has since grown to be the $249 billion
industry it is today.

Industry structure
Rank

Rank

Rank

Rank

2012

2011

2010

2009

Company

Country of
origin

Revenue
(million
$ USD)

2012/2011
changes

Market share

Intel Corporation

United States

$47,543

-2.4%

15.7%

Samsung Electronics

South Korea

$30,474

+6.7%

10.1%

Qualcomm

United States

$12,976

+27.2%

4.3%

Texas Instruments

United States

$12,008

-14.0%

4.0%

Toshiba Semiconductors

Japan

$10,996

-13.6%

3.6%

Renesas Electronics

Japan

$9,430

-11.4%

3.1%

Hynix

South Korea

$8,462

-8.9%

2.8%

STMicroelectronics

France / Italy

$8,453

-13.2%

2.8%

10

10

14

Broadcom

United States

$7,840

+9.5%

2.6%

10

13

Micron Technology

United States

$6,955

-5.6%

2.3%

Source:iSuppli Corporation supplied rankings for 2010 (Semiconductor foundries are excluded)

Ran
Rank
k
2013 201
2

Company

Country of
origin

Revenue
(million
$USD)

2013/2012
changes

Market share

Intel Corporation(1)

USA

46 960

-1.0%

14.8%

Samsung Electronics
(2)

South Korea

33 456

+7.0%

10.5%

Qualcomm

USA

17 341

+31.6%

5.5%

10

Micron Technology(3)

USA

14 168

+109.2%

4.5%

SK Hynix

South Korea

13 335

+48.7%

4.2%

12 459

+11.9%

3.9%

Toshiba Semiconducto Japan

r
Texas Instruments
USA

11 379

-5.5%

3.6%

Broadcom

USA

8 121

+3.5%

2.6%

STMicroelectronics

FranceItaly

8 076

-4.9%

2.5%

10

Renesas Electronics(4) Japan

7 822

-15.3%

2.5%

Source:iSuppli Corporation supplied rankings for 2010 (Semiconductor foundries are excluded)

Wafer
A typicalwafer is made out of extremelypure

silicon
that
isgrown
intomono-crystalline
cylindricalingots (boules)up to 300mm (slightly
less
than
12inches)
in
diameter
using
theCzochralski process. These ingots are then
sliced into wafers about 0.75mm thick and
polished to obtain a very regular and flat surface.
Once the wafers are prepared, many process
steps are necessary to produce the desired
semiconductor integrated circuit. In general, the
steps can be grouped into two major parts:
Front-end-of-line (FEOL) processing
Back-end-of-line (BEOL)processing

Wafer Fabrication
Semiconductor device fabricationis the process

used to create theintegrated circuits that are

present in everydayelectrical andelectronic
devices.
A multiple-step sequence of photolithographic and
chemical processing steps during which electronic
circuits are gradually created on awafer made of
pure semiconducting material.Silicon is almost
always
used,
but
variouscompound
semiconductors
are
used
for
specialized
applications.
The entire manufacturing process, from start to
packaged chips ready for shipment, takes six to

Front-end-of-line (FEOL) processing

FEOL

processing refers to the formation of

thetransistors directly in thesilicon. The raw wafer
is engineered by the growth of an ultrapure, virtually
defect-free silicon layer throughepitaxy. In the most
advanced logic devices,prior to the silicon epitaxy
step, tricks are performed to improve the
performance of the transistors to be built. One
method involves introducing astraining stepwherein
a silicon variant such as silicon-germanium (SiGe)is
deposited. Once the epitaxial silicon is deposited,
the crystal lattice becomes stretched somewhat,
resulting in improved electronic mobility.

Another method, calledsilicon on insulator

technology involves the insertion of an insulating
layer between the raw silicon wafer and the thin
layer of subsequent silicon epitaxy. This method
results in the creation of transistors with reduced
parasitic effects.
Gate oxide and implants
Front-end surface engineering is followed by
growth of thegate dielectric (traditionallysilicon
dioxide), patterning of the gate, patterning of the
source and drain regions, and subsequent
implantation or diffusion of dopants to obtain the
desired complementary electrical properties.

Back-end-of-line (BEOL) processing

Metal layers
Once the various semiconductor devices have
been created, they must be interconnected to
form the desired electrical circuits. This occurs
in a series of wafer processing steps
collectively referred to as BEOL.
BEOL

processing involves creating metal

interconnecting wires that are isolated by
dielectric layers.

 The insulating material has traditionally been

a form of SiO2or asilicate glass, but recently

newlow dielectric constant materials are
being used (such assilicon oxycarbide),
typically providing dielectric constants around
2.7 (compared to 3.9 for SiO2), although
materials with constants as low as 2.2 are
being offered to chipmakers.

Back-end-of-line (BEOL) processing

Interconnect
Synthetic detail of a standard cell through
four layers of planarized copper interconnect,
down to the polysilicon (pink), wells (greyish)
and substrate (green).
Historically, the metal wires have been
composed ofaluminium. In this approach to
wiring (often calledsubtractive aluminium),
blanket films of aluminium are deposited first,
patterned, and then etched, leaving isolated
wires. Dielectric material is then deposited
over the exposed wires.

The various metal layers are interconnected by

etching holes (called "vias")in the insulating
material and then depositingtungsten in them with
aCVD technique; this approach is still used in the
fabrication of many memory chips such asdynamic
random access memory(DRAM), because the
number of interconnect levels is small (currently no
more than four).
More recently, as the number of interconnect levels
for logic has substantially increased due to the
large number of transistors that are now
interconnected in a modernmicroprocessor, the
timing delay in the wiring has become so
significant as to prompt a change in wiring material
(from aluminium tocopper layer) and a change in