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its switching elements are vacuum tubes (a big advance from relays)
50G
1G
500M
120M
10M
1M
80000
3000
500
100
1950
1955
1960
1965
1970
1975
1980
1985
1990
RAM
ROM
Micro
processor
Address
Data
Control
Lines
Input
Output
MPU
Internal Registers:
Arithmetic-Logic Unit
Timing & Control Unit
Address, Data, Control Buses
Instruction Decoder
6502 Microprocessor
Internal
Registers:
MPU
Data
Address
Register,
Program
Counter,
Data
Register,
Accumulator,
Instruction
Reg.
ArithmeticLogic Unit
Timing &
Control Unit
Address, Data,
Control Buses
Instruction
Decoder
DAR
PC
DR
ALU
IR
ID
T&C
Control
bus [8]
Analysis versus
Design
Analysis
Design / Synthesis
input
X
Digital Circuit
output
y
input
X
Digital Circuit
output
y
+5
0
time
+5
0
time
I - Introduction
16
ADC
Transducer
Analog
input
Digital
system
CPU
DAC
Actuator
+2
Logic 0
+.8
time
Logic levels
Undefined region
is inherent
digital, not analog
amplification,
weak => strong
Standards
TTL
RS-232C
Logic 1 & 0
Yes
ON
TRUE
HI
mark
No
OFF
FALSE
LOW
space
4
H
3
2
Volts
OUTPUT
INPUT
Obvious reasons
I - Introduction
26
Embedded products
Scientific equipment
I - Introduction
27
I - Introduction
28
example: digital logic where voltage < 0.8v is a 0 and > 2.0v is a 1
example: pair of transmission wires where a 0 or 1 is distinguished by
which wire has a higher voltage (differential)
example: orientation of magnetization signifies a 0 or a 1
store a value
recall a previously stored value
sense
AND
I - Introduction
drive
29
Scale
Time
Cost
I - Introduction
30
EE 171:
concepts/skills/abilities
Understanding the basics of logic design (concepts)
New ability: to accomplish the logic design task with the aid of computer-ai
design tools and map a problem description into an implementation with
programmable logic devices after validation via simulation and understand
of the advantages/disadvantages as compared to a software implementati
I - Introduction
38
I - Introduction
39
Z
close switch (if A is 1 or asserted)
and turn on light bulb (Z)
Z
open switch (if A is 0 or unasserted)
and turn off light bulb (Z)
Z A
I - Introduction
40
Z A and B
A
OR
Z A or B
I - Introduction
41
Switching networks
Switch settings
I - Introduction
42
Relay networks
A simple way to convert between conducting paths and
switch settings is to use (electro-mechanical) relays.
What is a relay?
conducting
path composed
of switches
closes circuit
current flowing through coil
magnetizes core and causes normally
closed (nc) contact to be pulled open
when no current flows, the spring of the contact
returns it to its normal position
43
Transistor networks
I - Introduction
44
MOS transistors
MOS transistors have three terminals: drain,
gate, and source
n-channel
open when voltage at G is low
closes when:
voltage(G) > voltage (S) +
I - Introduction
p-channel
closed when voltage at G is low
opens when:
voltage(G) < voltage (S)
45
MOS networks
X
what is the
relationship
between x and y?
3v
Y
0v
0 volts
3 volts
3 volts
0 volts
I - Introduction
46
3v
Z1
0v
what is the
relationship
between x, y and z?
x
z1
z2
3v
Z2
0v
I - Introduction
47
I - Introduction
48
PMOS
NMOS
How CMOS
Inverter
works?
CMOS Inverter
The concept of
multiplexer
Truth tables
This is a
truth table
of a
Multiplexer
Logic diagrams
This is a logic
diagram of a
Multiplexer
Multiplexer
Design using
MOS
transistors
S*AN
B*A
Negated S
Equations: Z = SA+ SB
A,B,Z have 4 bits each
Hardware description
languages
Various hardware
description languages
ABEL
VHDL
61
State 0
State 1
Relay logic
Circuit Open
Circuit Closed
CMOS logic
0.0-1.0 volts
2.0-3.0 volts
Transistor transistor logic (TTL)
0.0-0.8 volts 2.0-5.0 volt
Fiber Optics
Light off
Light on
Dynamic RAM
Discharged capacitor
Charged ca
Nonvolatile memory (erasable)
Trapped electrons
No
Programmable ROM
Fuse blown
Fuse intact
Bubble memory
No magnetic bubble
Bubble pres
Magnetic disk
No flux reversal
Flux reversal
Compact disc
No pit
Pit
I - Introduction
62
inputs
system
outputs
I - Introduction
63
AND, NAND
A
B
OR, NOR
A
B
easy to implement
with CMOS transistors
(the switches we have
available and use most)
64
Sequential logic
Sequential systems
I - Introduction
65
I - Introduction
66
Combinational:
input A, B
wait for clock edge
observe C
wait for another clock edge
observe C again: will stay the same
Sequential:
input A, B
wait for clock edge
observe C
wait for another clock edge
observe C again: may be different
I - Introduction
A
C
B
Clock
67
I - Introduction
68
An example of abstraction
Calendar subsystem: number of days in a
month (to control watch display)
I - Introduction
69
Implementation of calendar
subsystem in software
integer number_of_days ( month,
leap_year_flag) {
switch (month) {
case 1: return (31);
case 2: if (leap_year_flag == 1) then return (29)
else return (28);
case 3: return (31);
...
case 12: return (31);
default: return (0);
}
I - Introduction
70
Implementation
as a subsystem
Implementation
of calendar
combinational
digital system circuit
in hardware
as a combinational
Encoding:
Behavior:
combinational
truth table
specification
month
leap
month
0000
0001
0010
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
111
leap
0
1
d28
0
1
0
0
0
0
0
0
0
0
0
0
0
d29
0
0
1
0
0
0
0
0
0
0
0
0
0
d30
0
0
0
0
1
0
1
0
0
1
0
1
0
d31
1
0
0
1
0
1
0
1
1
0
1
0
1
d28d29d30d31
I - Introduction
71
symbol
for not
symbol
for and
I - Introduction
symbol
for or
month
0001
0010
0010
0011
0100
...
1100
1101
111
0000
leap
0
1
d28
0
1
0
0
0
d29
0
0
1
0
0
d30
0
0
0
0
1
d31
1
0
0
1
0
72
Activity
How much can we simplify d31?
m8 is 0 and m1 is 1, or m8 is 1 and m1 is 0
d31 = m8m1 + m8m1
Activity
d31 is true if:
m8 is 0 and m1 is 1, or m8 is 1 and m1 is 0
d31 = m8m1 + m8m1
I - Introduction
76
Another example of
combinational circuit
Door combination lock:
I - Introduction
77
I - Introduction
78
Encoding:
Behavior:
new
value
reset
state
open/closed
I - Introduction
79
ERR
closed
C1!=value
& new
S1
reset
closed
closed
C1=value
& new
not new
I - Introduction
S2
C2!=value
& new
S3
C3!=value
& new
closed
C2=value
& new
not new
OPEN
open
C3=value
& new
not new
80
control
new
value
C1
C2
multiplexer
C3
mux
control
equal
reset
controller
clock
comparator
equal
I - Introduction
open/closed
81
ERR
closed
not equal
& new
reset
not equal
not equal
& new
& new
S1
S2
S3
OPEN
closed
closed
closed
open
mux=C1 equal mux=C2 equal mux=C3 equal
& new
& new
& new
not new
I - Introduction
not new
not new
82
reset
1
0
0
0
0
0
0
0
0
0
0
0
new
0
1
1
0
1
1
0
1
1
I - Introduction
equal
0
1
0
1
0
1
state
S1
S1
S1
S2
S2
S2
S3
S3
S3
OPEN
ERR
next
state
S1
S1
ERR
S2
S2
ERR
S3
S3
ERR
OPEN
OPEN
ERR
closed
not equal
not equal not equal
& new
& new
& new
S1
S2
S3
OPEN
closed
closed
closed
open
mux=C1 equal mux=C2 equal mux=C3 equal
& new
& new
& new
not new
mux
C1
C1
C2
C2
C3
C3
ERR
not new
not new
open/closed
closed
closed
closed
closed
closed
closed
closed
closed
closed
open
open
closed
83
I - Introduction
84
choose 1 bits: 1, 0
I - Introduction
reset
1
0
0
0
0
0
0
0
0
0
0
0
new
0
1
1
0
1
1
0
1
1
equal
0
1
0
1
0
1
state
0001
0001
0001
0010
0010
0010
0100
0100
0100
1000
0000
next
state
0001
0001
0000
0010
0010
0000
0100
0100
0000
1000
1000
0000
mux
001
001
010
010
100
100
open/closed
0
0
0
good choice of encoding!
0
0
mux is identical to
0
last 3 bits of state
0
0
open/closed is
0
identical to first bit
1
of state
1
0
85
Activity
Have lock always wait for 3 key presses
exactly before making a decision
remove reset
not new
not new
E2
closed
not equal
& new
E3
new
not equal
& new
closed
new
ERR
closed
not equal
& new
S1
S2
S3
closed
closed
closed
mux=C1 equal mux=C2 equal mux=C3 equal
& new
& new
& new
not new
I - Introduction
not new
OPEN
open
not new
86
equal
reset
controller
clock
comb. logic
state
clock
open/closed
I - Introduction
87
Design hierarchy
system
control
data-path
code
registers multiplexer comparator
register
state
registers
combinational
logic
logic
switching
networks
I - Introduction
88
Summary
I - Introduction
89
Number Systems
Positional-Value System
The value of a digit (digit from Latin word for
finger) depends on its position
Positional values
2 1 0
(weights)
10 10 10
-1
-2
-3
10 10 10
5 6 7 . 9 1 4
MSD
Decimal
point
We will write ( 5 6 7. 9 1 4)10
LSD
Binary:
Base-2 Number System
5 4 3 2 1 0
2 2 2 2 2 2
-1 -2 -3
2 2 2
1 0 1 1 1 1 . 0 0 1
Conversion ( ) I
( )10
( )2
( )4
( )8
( )16
. A
Convert ( ) 10
( )r
Integer part:
Fractional part: