Beruflich Dokumente
Kultur Dokumente
CSIR-CEERI
Principle Scientist
Reconfigurable Computing Systems Lab
&
Wireless Sensor Network Systems Lab
Digital Systems Group
CSIR - CENTRAL ELECTERONICS ENGINEERING RESEARCH INSTITUTE (CSIR - CEERI),
Pilani-333031, Rajasthan.
ARM
1 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 1
Addressing Mode 1 - Data-processing operands (Immediate and Register, with and without shift)
Addressing Mode 2 - Load and Store Word or Unsigned Byte (Immediate offset, Register offset, Scaled
register offset, Immediate pre-indexed, Register pre-indexed, Scaled register pre-indexed, Immediate
post-indexed, Register post-indexed, Scaled register post-indexed)
Addressing Mode 3 - Miscellaneous Loads and Stores (Immediate offset, Register offset, Immediate pre-
Store Multiple instructions store a subset (possibly all) of the general-purpose registers to memory
Addressing Mode 5 - Load and Store Coprocessor (Immediate offset, Immediate pre-indexed, Immediate
post-indexed, Unindexed)
ARM
2 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 2
classes of instruction
Data-processing instructions
Branch instructions
Data-processing instructions
Arithmetic/logic instructions
Comparison instructions
Single Instruction Multiple Data (SIMD) instructions
Multiply instructions
Miscellaneous Data Processing instructions
Coprocessor instructions
These start a coprocessor-specific internal
operation.
Data transfer instructions
These transfer coprocessor data to or from memory.
The address of the transfer is calculated by the
ARM processor.
Register transfer instructions
These allow a coprocessor value to be transferred
to or from an ARM register, or a pair of ARM
registers.
Exception-generating instructions
Software interrupt instructions
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 3
Fig. 1. (a)
Fig. 2. (a)
Fig. 2. (a)
ARM
4 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 4
Fig. 3. (a)
Fig. 3. (b)
Fig. 4. (a)
Fig. 4. (b)
ARM
5 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 5
Addressing Mode 1 - Data-processing operands (Immediate and Register, with and without shift)
There are 11 formats used to calculate the <shifter_operand> in an ARM data-processing instruction
The general instruction syntax is:
<opcode>{<cond>}{S} <Rd>, <Rn>, <shifter_operand>
Register
Immediate
where <shifter_operand> is one of the following:
1. #<immediate>
Data-processing operands - Immediate
2. <Rm>, LSL #<shift_imm>
Data-processing operands - Logical shift left by immediate
3. <Rm>, LSR #<shift_imm>
Data-processing operands - Logical shift right by immediate
5. <Rm>, ASR #<shift_imm>
Data-processing operands - Arithmetic shift right by immediate
6. <Rm>, ROR #<shift_imm>
Data-processing operands - Rotate right by immediate
7. <Rm>, RRX
Data-processing operands - Rotate right with extend
ARM
6 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 6
CSIR-CEERI
S bit Indicates that the instruction updates the condition codes.; Rd Specifies the destination register; Rn Specifies the first source
operand register.
The <shifter_operand> value is formed by rotating (to the right) an 8-bit immediate value to any
even bit position in a 32-bit word. If the rotate immediate is zero, the carry-out from the shifter is
the value of the C flag, otherwise, it is set to bit[31] of the value of <shifter_operand>.
Specifies the immediate constant wanted. It is encoded in the instruction as
an 8-bit immediate (immed_8) and a 4-bit immediate (rotate_imm), so that
<immediate> is equal to the result of rotating immed_8 right by (2
rotate_imm) bits <opcode>{<cond>}{S} <Rd>, <Rn>, <shifter_operand>
Immediate:
ADD r0, r1, #0xFF
With rotate-right
ADD r0,r1, #0xFF, 28
(Rotate value must be even: #0xFF ROR 28 generates:0XFF00000000)
ARM
7 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 7
CSIR-CEERI
S bit Indicates that the instruction updates the condition codes.; Rd Specifies the destination register; Rn Specifies the first source
operand register.
ARM
8 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 8
CSIR-CEERI
Calculate the rotation necessary to generate the constant 4080 using the byte rotation scheme.
solution:
Since 4080 is 111111110000, the byte 11111111 or 0xFF can be rotated to the left by four bits. However,
the rotation scheme rotates a byte to the right; therefore, a rotation factor of 28 is needed, since rotating to
the left n bits is equivalent to rotating to the right by (32-n) bits. The ARM instruction would be
MOV
ARM
9 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
ARM
10 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 10
CSIR-CEERI
Syntax
<Rm>, LSL #<shift_imm>; where: <Rm> Specifies the register whose value is to be shifted; LSL = a logical shift left.
<shift_imm> Specifies the shift. This is a value between 0 and 31.
Default shift If the value of <shift_imm> == 0, the operand can be written as just <Rm>
ARM
11 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 11
ARM
12 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
CSIR-CEERI
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 12
CSIR-CEERI
Syntax
<Rm>, LSR #<shift_imm>; where: <Rm> Specifies the register whose value is to be shifted; LSL = a logical shift
right.
<shift_imm> Specifies the shift. This is an immediate value between 1 and 32. (A shift by 32 is encoded by shift_imm
== 0.)
ARM
13 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 13
CSIR-CEERI
Syntax
<Rm>, ASR #<shift_imm>;
where: <Rm> Specifies the register whose value is to be shifted; ASR = arithmetic shift right
<shift_imm> Specifies the shift. This is an immediate value between 1 and 32. (A shift by 32 is encoded by shift_imm
== 0.)
Operation
ARM
14 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 14
CSIR-CEERI
Syntax
<Rm>, ROR #<shift_imm>;
where: <Rm> Specifies the register whose value is to be shifted; ROR = a rotate right
<shift_imm> Specifies the rotation. This is an immediate value between 1 and 31. When shift_imm == 0, an RRX
operation (rotate right with extend) is performed. This is described in Data-processing operands - Rotate right with
extend.
Operation
ARM
15 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 15
ARM
16 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
CSIR-CEERI
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 16
CSIR-CEERI
Syntax
<Rm>, RRX ;
where: <Rm> Specifies the register whose value is shifted right by one bit; RRX = a rotate right with extend
Operation
ARM
17 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 17
Syntax
<Rm>, LSL <Rs>
where: <Rm> Specifies the register whose value is to be shifted.
<Rs> Is the register containing the value of the shift.
CSIR-CEERI
ARM
18 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 18
Syntax
where:
<Rm>
<Rm> Specifies the register whose value is to be shifted.
ARM
19 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 19
Syntax
<Rm>, LSL <Rs>
where: <Rm> Specifies the register whose value is to be shifted.
<Rs> Is the register containing the value of the shift.
CSIR-CEERI
ARM
20 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 20
Syntax
CSIR-CEERI
ARM
21 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 21
Syntax
<Rm>, LSR <Rs>
where: <Rm> Specifies the register whose value is to be shifted.
<Rs> Is the register containing the value of the shift.
CSIR-CEERI
ARM
22 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 22
Syntax
<Rm>, ASR <Rs>
where: <Rm> Specifies the register whose value is to be shifted.
<Rs> Is the register containing the value of the shift.
CSIR-CEERI
ARM
23 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 23
Syntax
<Rm>, ROR <Rs>
where: <Rm> Specifies the register whose value is to be shifted.
<Rs> Is the register containing the value of the rotation.
CSIR-CEERI
ARM
24 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 24
Constant Multiplication:
Constant multiplication is often faster using shifts
and additions
Constant division
MOV r1, r3, ASR #7 ; r1 = r3/128
Treats the register value like signed values (shifts in MSB).
Vs.
MOV r1, r3, LSR #7 ; r1 = r3/128
Treats register value like unsigned values (shifts in 0)
ARM
25 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
Constant Multiplication:
with subtractions
Multiply by 35:
ADD
RSB
r9,r8,r8,LSL #2 ; r9=r8*5
r10,r9,r9,LSL #3 ; r10=r9*7
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 25
CSIR-CEERI
There are nine formats used to calculate the address for a Load and Store Word or Unsigned Byte
instruction.
The syntax is: LDR|STR{<cond>}{B}{T} <Rd>, <addressing_mode>
where <addressing_mode> is one of the nine options listed below.
1. [<Rn>, #+/-<offset_12>]
Load and Store Word or Unsigned Byte - Immediate offset.
2. [<Rn>, #+/-<offset_12>]!
Load and Store Word or Unsigned Byte - Immediate pre-indexed with auto update.
3. [<Rn>], #+/-<offset_12>
Load and Store Word or Unsigned Byte - Immediate post-indexed.
pre-indexed = Offset
pre-indexed with auto update = Pre-Index Addressing with Auto Index =
Pre-index write back = Pre-index with write back = Auto Index
ARM
26 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 26
CSIR-CEERI
Register
1. [<Rn>, +/-<Rm>]
Load and Store Word or Unsigned Byte - Register offset (pre-index).
2. [<Rn>, +/-<Rm>, <shift> #<shift_imm>]
Load and Store Word or Unsigned Byte - Scaled register offset (pre-index).
3. [<Rn>, +/-<Rm>]!
Load and Store Word or Unsigned Byte - Register pre-indexed with auto update.
4. [<Rn>], +/-<Rm>
Load and Store Word or Unsigned Byte - Register post-indexed.
5. [<Rn>], +/-<Rm>, <shift> #<shift_imm>
Load and Store Word or Unsigned Byte - Scaled register post-indexed
6. [<Rn>, +/-<Rm>, <shift> #<shift_imm>]!
Load and Store Word or Unsigned Byte - Scaled register pre-indexed with auto update.
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 27
Load and Store Word or Unsigned Byte: Pre and Post Index
CSIR-CEERI
without a writeback
Auto-indexing addressing (LDR
ARM
28 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 28
LDR
@ R0=mem[R1+4]
@ R1 unchanged
R1
+
R0
ARM
29 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 29
Load and Store Word or Unsigned Byte: Pre and Post Index
CSIR-CEERI
LDR
Immediate
ARM
30 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 30
ARM
31 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 31
LDR
@ R0=mem[R1+4]
@ R1=R1+4
R1
]!
+
R0
ARM
32 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 32
ARM
33 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 33
Post-index addressing
LDR
R0, R1, #4
CSIR-CEERI
@ R0=mem[R1]
@ R1=R1+4
LDR R0,[R1],
R0
R1
+
ARM
34 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 34
ARM
35 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 35
CSIR-CEERI
There are nine formats used to calculate the address for a Load and Store Word or Unsigned Byte
instruction.
The syntax is: LDR|STR{<cond>}{B}{T} <Rd>, <addressing_mode>
where <addressing_mode> is one of the nine options listed below.
1. [<Rn>, #+/-<offset_12>] Immediate
Load and Store Word or Unsigned Byte - Immediate offset.
2. [<Rn>, #+/-<offset_12>]!
Load and Store Word or Unsigned Byte - Immediate pre-indexed with auto update.
3. [<Rn>], #+/-<offset_12>
Load and Store Word or Unsigned Byte - Immediate post-indexed.
ARM
36 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 36
CSIR-CEERI
Syntax [<Rn>, #+/-<offset_12>]; where: <Rn> Specifies the register containing the base address. <offset_12> Specifies the immediate
offset used with the value of Rn to form the address.
The B bit This bit distinguishes between an unsigned byte (B==1) and a word (B==0) access.
The L bit This bit distinguishes between a Load (L==1) and a Store (L==0) instruction.
Use of R15 If R15 is specified as register Rn, the value used is the address of the instruction plus eight.
ARM
37 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 37
Addressing Mode 2 - Load and Store Word or Unsigned Byte (Immediate pre-indexed auto update)
The B bit This bit distinguishes between an unsigned byte (B==1) and a word (B==0) access.
The L bit This bit distinguishes between a Load (L==1) and a Store (L==0) instruction.
Use of R15 Specifying R15 as register Rn has UNPREDICTABLE results.
ARM
38 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 38
CSIR-CEERI
The B bit This bit distinguishes between an unsigned byte (B==1) and a word (B==0) access.
The L bit This bit distinguishes between a Load (L==1) and a Store (L==0) instruction.
Use of R15 Specifying R15 as register Rn has UNPREDICTABLE results.
ARM
39 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 39
CSIR-CEERI
There are six formats used to calculate the address for load and store (signed or unsigned) half word,
load signed byte, or load and store double word instructions.
The general instruction syntax is: LDR|STR{<cond>}H|SH|SB|D <Rd>, <addressing_mode>
where <addressing_mode> is one of the following six options:
1. [<Rn>, #+/-<offset_8>]
2.
[<Rn>, +/-<Rm>]
3.
[<Rn>, #+/-<offset_8>]!
4.
[<Rn>, +/-<Rm>]!
5.
[<Rn>], #+/-<offset_8>
6.
[<Rn>], +/-<Rm>
ARM
40 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 40
CSIR-CEERI
ARM
41 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 41
CSIR-CEERI
ARM
42 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 42
CSIR-CEERI
The U bit Indicates whether the offset is added to the base (U == 1) or subtracted from the base (U == 0).
The W bit Has two meanings:
P == 0 The W bit must be 0 or the instruction is UNPREDICTABLE.
P == 1 W == 1 indicates that the memory address is written back to the base register
(pre-indexed addressing), and W == 0 that the base register is
unchanged (offset addressing).
Unsigned bytes
If S == 0 and H == 0, apparently indicating an unsigned byte,
Unsigned bytes are accessed by the LDRB, LDRBT, STRB and STRBT instructions, which use
addressing mode 2 rather than addressing mode 3.
Signed stores If S ==1 and L == 0, apparently indicating a signed store instruction, the encoding along
with the H-bit is used to support the LDRD (H == 0) and STRD (H == 1) instructions.
ARM
43 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 43
CSIR-CEERI
Load and Store Multiple addressing modes produce a sequential range of addresses. The lowestnumbered register is stored at the lowest memory address and the highest-numbered register at the
highest memory address
The general instruction syntax is: LDM|STM{<cond>}<addressing_mode> <Rn>{!}, <registers>{^}
where <addressing_mode> is one of the following the options:
1. IA (Increment After)
2. IB (Increment Before)
3. DA (Decrement After)
4. DB (Decrement Before)
ARM
44 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 44
ARM
45 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
CSIR-CEERI
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 45
CSIR-CEERI
indicates that the word addressed by Rn is excluded from the range of memory
locations accessed, and lies one word beyond the top of the range (U==0) or one
word below the bottom of the range (U==1).
The U bit Indicates that the transfer is made upwards (U==1) or downwards (U==0) from the base register.
The S bit
For LDMs that load the PC, the S bit indicates that the CPSR is loaded from the SPSR.
For LDMs that do not load the PC and all STMs, the S bit indicates that when the
processor is in a privileged mode, the User mode banked registers are transferred instead
of the
registers of the current mode.
LDM with the S bit set is UNPREDICTABLE in User or System mode.
ARM
46 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 46
CSIR-CEERI
The W bit
Indicates that the base register is updated after the transfer. The base register is
incremented (U==1) or decremented (U==0) by four times the number of registers
in the
register list.
The L bit
Register list
The register_list field of the instruction has one bit for each general-purpose
register: bit[0] for register zero through to bit[15] for register 15 (the PC). If no
bits are set,
the result is UNPREDICTABLE.
The instruction syntax specifies the registers to load or store in <registers>,
which is a comma-separated list of registers, surrounded by { and }.
ARM
47 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 47
CSIR-CEERI
There are four addressing modes which are used to calculate the address of a Load or Store
Coprocessor instruction.
The general instruction syntax is: <opcode>{<cond>}{L} <coproc>,<CRd>,<addressing_mode>
where <addressing_mode> is one of the following the options:
1. [<Rn>,#+/-<offset_8>*4]
Load and Store Coprocessor - Immediate offset
2. [<Rn>,#+/-<offset_8>*4]!
3. [<Rn>],#+/-<offset_8>*4
4. [<Rn>],<option>
ARM
48 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 48
CSIR-CEERI
The U bit
The N bit
The meaning of this bit is coprocessor-dependent. Its recommended use is to
distinguish between different-sized values to be transferred.
ARM
49 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 49
CSIR-CEERI
(W
ARM
50 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 50
CSIR-CEERI
Break
ARM
51 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 51
classes of instruction
Branch instructions
Data-processing instructions
Status register transfer instructions transfer the contents of
Instruction formats
A. Data Processing Instructions
B. Single Data Swap
C. Shift and Rotate Instructions
D. Unconditional Instructions and Conditional
Instructions:
E. Stack Operations
F. Branch
G. Multiply Instructions
E: Data Transfer
ARM
52 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 52
Data Types
CSIR-CEERI
Data type
Size
Signed range
Unsigned range
Byte
-128 to 127
0 to 255
Half word
-32768 to 32767
0 to 65535
Word
-2147483648 to
2147483647
0 to 4294967295
Double word
-263 to 263-1
0 to 264-1
float
Word
Double word
-1.7976931348623157 10308 to
1.7976931348623157 10308
pointers
Word
0x00 to 0xFFFFFFFF
enum
Byte
True or false
wchar_t
Half word
0 to 65535
ARM
53 University Program
Copyright
ARM Ltd 2013
solomon@ceeri.ernet.in,
/ kota_solomonraju@yahoo.co.uk
EEE G512_ Embedded Systems Design: ARM Architectures; RCS & WSN LABs, DSG, CSIRCEERI, Pilani 53