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You are on page 1of 34

Design Procedure

Specification

Formulation - Obtain a state diagram or state table

State Assignment - Assign binary codes to the states

Flip-Flop Input Equation Determination - Select flip-flop

types and derive flip-flop equations from next state entries in the

table

from output entries in the table

Technology Mapping - Find circuit from equations and map to

flip-flops and gate technology

Chapter 5 - Part 2 1

In specifying a circuit, we use states to remember

meaningful properties of past input sequences that are

essential to predicting future output values.

A sequence recognizer is a sequential circuit that

produces a distinct output value whenever a prescribed

pattern of input symbols occur in sequence, i.e,

recognizes an input sequence occurence.

We will develop a procedure specific to sequence

recognizers to convert a problem statement into a state

diagram.

Next, the state diagram, will be converted to a state

table from which the circuit will be designed.

Chapter 5 - Part 2 2

Initial state

When the power in a digital system is first

turned on, the state of the flip-flop is unknown.

In this chapter, the circuits we design must

have known initial state

Reset or master reset is needed.

Asynchronous reset

Synchronous reset

Fig 5-19

Chapter 5 - Part 2 3

Example: Recognize the sequence 1101

Note that the sequence 1111101 contains 1101 and "11" is a proper

sub-sequence of the sequence.

first two one's have occurred as it receives another

symbol.

Also, the sequence 1101101 contains 1101 as both an initial

subsequence and a final subsequence with some overlap, i.

e., 1101101 or 1101101.

And, the 1 in the middle, 1101101, is in both subsequences.

The sequence 1101 must be recognized each time it occurs

in the input sequence.

Chapter 5 - Part 2 4

Define states for the sequence to be recognized:

assuming it starts with first symbol,

continues through each symbol in the sequence to be recognized,

and

uses output 1 to mean the full sequence has occurred,

with output 0 otherwise.

Add a state that

recognizes

the first "1."

1/0

State "A" is the initial state, and state "B"A

B

is the state which

represents the fact that the "first" one in the input subsequence

has occurred. The output symbol "0" means that the full

recognized sequence has not yet occurred.

Chapter 5 - Part 2 5

After one more 1, we have:

C is the state obtained

when the input sequence

has two "1"s.

A 1/0

1/0

1/0

0/0

1/1

A 1/0 B

D

C

Transition arcs are used to denote the output function (Mealy Model)

Output 1 on the arc from D means the sequence has been recognized

To what state should the arc from state D go? Remember: 1101101 ?

Note that D is the last state but the output 1 occurs for the input

applied in D. This is the case when a Mealy model is assumed.

Chapter 5 - Part 2 6

A 1/0

1/0

0/0

1/1

1101 is a sub-sequence of 1101. It follows a 0

which is not a sub-sequence of 1101. Thus it

should represent the same state reached from the

initial state after a first 1 is observed. We obtain:

1/0

0/0

1/0

A

B

C

D

1/1

Chapter 5 - Part 2 7

A

1/0

1/0

0/0

1/1

The state have the following abstract meanings:

A: No proper sub-sequence of the sequence has

occurred.

B: The sub-sequence 1 has occurred.

C: The sub-sequence 11 has occurred.

D: The sub-sequence 110 has occurred.

The 1/1 on the arc from D to B means that the last 1

has occurred and thus, the sequence is recognized.

Chapter 5 - Part 2 8

The other arcs are added to each state for

inputs not yet listed. Which arcs are missing?

A

1/0

1/0

0/0

Answer:

1/1

"0" arc from A

"0" arc from B

"1" arc from C

"0" arc from D.

Chapter 5 - Part 2 9

State transition arcs must represent the fact that

an input subsequence has occurred. Thus we

get:

0/0

1/0

1/0

1/0

0/0

0/0

1/1

0/0

that State C means two or more 1's have occurred.

Chapter 5 - Part 2 10

From the State Diagram, we can fill in the State Table.

There are 4 states, one

input, and one output.

We will choose the form

with four rows, one for

each current state.

From State A, the 0 and

1 input transitions have

been filled in along with

the outputs.

0/0

A

1/0

1/0

1/0

0/0

0/0

1/1

0/0

Present

State

A

B

C

D

Next State

x=0 x=1

Output

x=0 x=1

Chapter 5 - Part 2 11

From the state diagram, we complete the

state table.

0/0

A

1/0

1/0

0/0

Present

State

A

B

C

D

Next State

x=0 x=1

A

B

A

C

D

C

A

B

Output

x=0 x=1

0

0

0

0

0

0

0

1

1/0

C

0/0

1/1

0/0

like for the Moore model?

Chapter 5 - Part 2 12

For the Moore Model, outputs are associated with

states.

We need to add a state "E" with output value 1

for the final 1 in the recognized input sequence.

This new state E, though similar to B, would generate

an output of 1 and thus be different from B.

usually has more states than the Mealy model.

Chapter 5 - Part 2 13

0

1

We mark outputs on

states for Moore model

0

1

1

A/0

B/0

C/0

Arcs now show only

state transitions

0

1

1

Add a new state E to

0

E/1

produce the output 1

Note that the new state,

0

E produces the same behavior

in the future as state B. But it gives a different output

at the present time. Thus these states do represent a

D/0

Chapter 5 - Part 2 14

The state table is shown

below

0

A/0

state in the Moore model:

Moore is More.

Present

State

A

B

C

D

E

Next State

x=0 x=1

A

B

A

C

D

C

A

E

A

C

1

1

B/0 1

0

1

0

Output

y

0

0

0

0

1

C/0

D/0

E/1

0

Chapter 5 - Part 2 15

State Assignment

Counting Order Assignment: A = 0 0, B = 0 1, C

= 1 0, D = 1 1

The resulting coded state table:

Present Next State

Output

State x = 0 x = 1 x = 0 x = 1

00

01

10

11

00

00

11

00

01

10

10

01

0

0

0

0

0

0

0

1

Chapter 5 - Part 2 16

Gray Code Assignment: A = 0 0, B = 0 1, C = 1

1, D = 1 0

The resulting coded state table:

Present Next State

Output

State x = 0 x = 1 x = 0 x = 1

00

01

11

10

00

00

10

00

01

11

11

01

0

0

0

0

0

0

0

1

Chapter 5 - Part 2 17

Gray Code Assignment

Assume D flip-flops (two is needed for 4 states)

Obtain K-maps for DA, DB, and Z:

Chapter 5 - Part 2 18

Implementation

Gate input cost:

combinational logic: 9

flip-flop: 28 (=142)

total: 37

Circuit:

A

D

C

R

Z

X

Clock

Reset

D

C

R

Chapter 5 - Part 2 19

One-Hot Assignment : A = 0001, B = 0010, C =

0100, D = 1000 The resulting coded state table:

Present Next State

State x = 0 x = 1

0001

0010

0100

1000

0001

0001

1000

0001

0010

0100

0100

0010

Output

x=0x=1

0

0

0

0

0

0

0

1

Chapter 5 - Part 2 20

Implementation

A(t 1) D A AX BX CX

( A B D) X

B(t 1) DB AX CX

( A C) X

C (t 1) DC BX CX

(B C) X

D(t 1) DD C X

Z DX

Chapter 5 - Part 2 21

Verification

Chapter 5 - Part 2 22

J-K and T flip-flops

Behavior

Implementation

using different flip-flop types

Characteristic tables

Characteristic equations

Excitation tables

For actual use, see Reading Supplement - Design

and Analysis Using J-K and T Flip-Flops

Chapter 5 - Part 2 23

J-K Flip-flop

Behavior

Same as S-R flip-flop with J analogous to S and K

analogous to R

Except that J = K = 1 is allowed, and

For J = K = 1, the flip-flop changes to the opposite

state

As a master-slave, has same 1s catching behavior

as S-R flip-flop

If the master changes to the wrong state, that state

will be passed to the slave

E.g., if master falsely set by J = 1, K = 1 cannot reset it

during the current clock cycle

Chapter 5 - Part 2 24

Implementation

Symbol

To avoid 1s catching

behavior, one solution

used is to use an

edge-triggered D as

the core of the flip-flop

J

C

K

J

K

D

C

Chapter 5 - Part 2 25

T Flip-flop

Behavior

Has a single input T

For T = 0, no change to state

For T = 1, changes to opposite state

As a master-slave, has same 1s catching

behavior as J-K flip-flop

Cannot be initialized to a known state using the

T input

Reset (asynchronous or synchronous) essential

Chapter 5 - Part 2 26

T Flip-flop (continued)

Implementation

Symbol

To avoid 1s catching

behavior, one solution

used is to use an

edge-triggered D as

the core of the flip-flop

Chapter 5 - Part 2 27

Used in analysis

Characteristic table - defines the next state of

the flip-flop in terms of flip-flop inputs and

current state

Characteristic equation - defines the next state

of the flip-flop as a Boolean function of the flipflop inputs and the current state

Used in design

Excitation table - defines the flip-flop input

variable values as function of the current state

and next state

Chapter 5 - Part 2 28

D Flip-Flop Descriptors

Characteristic Table

D

Q(t+1) Operation

0

1

0

1

Reset

Set

Characteristic Equation

Q(t+1) = D

Excitation Table

Q(t+1)

0

1

Operation

0

1

Reset

Set

Chapter 5 - Part 2 29

T Flip-Flop Descriptors

Characteristic Table

T Q(t+1) Operation

0

Q(t)

No change

Q(t)

Complement

Characteristic Equation

Q(t+1) = T Q

Excitation Table

Q(t 1)

Operation

Q(t)

No change

Q(t)

Complement

Chapter 5 - Part 2 30

Characteristic Table

S R Q(t+1) Operation

0 0

0 1

1 0

Q(t)

0

1

No change

Reset

Set

1 1

Undefined

Characteristic Equation

Q(t+1) = S + R Q, S.R = 0

Excitation Table

0

0

1

0

1

0

0 X No change

1 0 Set

0 1 Reset

X 0 No change

Chapter 5 - Part 2 31

Characteristic Table

J K Q(t+1) Operation

0

0

1

1

0

1

0

1

Q(t)

0

1

Q(t)

No change

Reset

Set

Complement

Characteristic Equation

Q(t+1) = J Q + K Q

Excitation Table

Q(t) Q(t+1) J K Operation

0

0

1

1

0

1

0

1

0

1

X

X

X

X

1

0

No change

Set

Reset

No Change

Chapter 5 - Part 2 32

Use the characteristic tables to find the output waveforms

for the flip-flops shown:

Clock

D,T

QD

D

C

QT

T

C

Chapter 5 - Part 2 33

(continued)

Use the characteristic tables to find the output waveforms

for the flip-flops shown:

Clock

S,J

R,K

S

C

R

QSR

QJK

Chapter 5 - Part 2 34

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