Microcontrollers

8051

Microprocessors:
General-purpose microprocessor

CPU for Computers

No RAM, ROM, I/O on CPU chip itself
Example Intels x86, Motorolas 680x0

CPU
GeneralPurpose
Microprocessor

Many chips on mothers board

Data Bus

RAM

ROM

I/O
Port

Address Bus
General-Purpose Microprocessor System

Timer

Serial
COM
Port

Microcontroller :
A smaller computer
On-chip RAM, ROM, I/O ports...
Example Motorolas 6811, Intels 8051, Zilogs Z8 and PIC 16X

CPU
I/O
Port

RAM ROM
Serial
Timer COM
Port

A single chip
Microcontroller

Microprocessor vs. Microcontroller

Microprocessor
CPU is stand-alone, RAM,
ROM, I/O, timer are separate
designer can decide on the
amount of ROM, RAM and
I/O ports.
expansive
versatility
general-purpose

Microcontroller
CPU, RAM, ROM, I/O and
timer are all on a single chip
fix amount of on-chip ROM,
RAM, I/O ports
for applications in which cost,
power and space are critical
single-purpose

Advantages over mp
Cost is lower
Standalone mp never used memory, I/O,
clock necessary
For mp- large size PCB
Large PCB- more effort and cost
Big physical size
More difficult to trouble shoot mp based
A mc is a mp with integrated peripherals.

Advantages of mc

Low cost
Small size of product
Easy to troubleshoot and maintain
More reliable
Additional mem, I/o can also be added
Software security feature
All features available with 40 pins.
Useful for small dedicated applications and not for larger
system designs which may require many more I/O ports.
Mostly used to implement small control functions.

Block Diagram
External interrupts
Interrupt
Control

On-chip
ROM for
program
code

Timer/Counter

On-chip
RAM

Timer 1
Timer 0

CPU

OSC

Bus
Control

4 I/O Ports

P0 P1 P2 P3

Address/Data

Serial
Port

TxD RxD

Counter
Inputs

Pin Description of the 8051

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(INT0)P3.2
(INT1)P3.3
(T0)P3.4
(T1)P3.5
(WR)P3.6
(RD)P3.7
XTAL2
XTAL1
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

8051
(8031)

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

Vcc
P0.0(AD0
P
) 0.1(AD1)
P0.2(AD2
P
) 0.3(AD3)
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
ALE/PROG
PSEN
P2.7(A15)
P2.6(A14
)P2.5(A13
P
) 2.4(A12
)P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)

Register Set of 8051-SFR

Special Function Registers (SFR) are
special purpose registers 21 in number
Addresses from 80H to FFH of all SFRs
Two 8 bit regist. A and B store operands
A, B, PSW, P0-P3, IP, IE, TCON,SCON
Bit addressable, 8bit each, 11 in number
SP, DPH,DPL,TMOD,TH0,TL0,TH1,TL1,SBUF,PCON
Byte addressable, 8bit each.
DPTR data pointer, accesses ext. mem. DPH + DPL = DPTR

Starting 32 bytes of RAM general purpose reg, divided

into 4 register banks of 8 registers each. Only one of
these bank accessible at one time. RS1 and RS0 of
PSW used to select bank.

Register Set of 8051-SFR

TH0-TL0 and TH1-TL1
16 bit timer registers

P0-P3 port latches

SP, PSW, IP Interrupt Priority, IE enable
TCON timer/counter control reg to turn on/off the
timers, interrupt control flags for ext. int like INT1 and
INT0
TMOD modes of operation of timer/counter
SCON serial port mode control reg
SBUF serial data buffer for transmit and receive
PCON Power control reg power down bit, idle bit

Registers
A
B
R0

DPTR

DPH

DPL

R1
R2

PC

PC

R3
R4
R5

Some 8051 16-bit Register hold

addresses

R6
R7
PSW (8)
Some 8-bitt Registers of
the 8051

SP (8)

8051 features
Internal ROM 4K, RAM 128bytes
Thirty two I/O pins as 4 8 bit ports P 0 P3
Two 16 bit timer/counters T0 and T1
Full duplex serial data receiver/trans. SBUF

Control registers TCON, TMOD, SCON,

PCON, IP and IE
Two external and three Internal Interrupt
sources
Oscillator and clock circuits

PCON
Idle mode oscillator, serial port, interrupt,
timer blocks are active but clock disabled.
Can be terminated with INT or reset
Power down mode on-chip osc stopped.
RAM contents preserved. Hardware reset
Two general purpose flags and a double
baud bit.

TMOD Register:

Gate : When set, timer

only runs while INT(0,1) is

high.

C/T : Counter/Timer select bit.

M1 : Mode bit 1.
M0 : Mode bit 0.

TCON Register:

TF1: Timer 1 overflow flag.

TR1: Timer 1 run control bit.
TF0: Timer 0 overflag.
TR0: Timer 0 run control bit.
IE1: External interrupt 1 edge flag.
IT1: External interrupt 1 type flag.
IE0: External interrupt 0 edge flag.
IT0: External interrupt 0 type flag.

Memory addressing

Program memory - EPROM

Intermediate results, variables, const
4KB internal from 0000 0FFFH
64KB external with PSEN, till FFFFH
Internal external difference PSEN

Data Memory RAM

64KB of external with DPTR signal
Internal memory two parts - 128 bytes Internal RAM
and secondly set of addresses from 80-FFH for
SFRs
128 bytes from 00 7FH direct or indirect
SFR addresses only direct addressing mode

Memory Addressing
Lower 128 bytes in three sections
00-1F 32 bytes 4 banks 00,01,10,11 each
containing 8 registers of 8 bits each. Only
one accessible at a time with PSW bits.
20-2FH 16bytes is bit addressable with
addresses 0F to 7FH, 20.7 or 20.0, or 0-7
30-7F 80 bytes of general purpose data
memory. It is byte addressable, used for
stack

 RAM memory space allocation in the 8051

7FH
Scratch pad RAM

30H
2FH
Bit-Addressable RAM
20H
1FH
18H
17H
10H
0FH
08H
07H
00H

Register Bank 3
Register Bank 2
Register Bank 1( Stack)
Register Bank 0

External I/O interfacing

8051 has two timers, one Serial i/o port
and 4 8bit addressable ports.
More I/O as external memory-mapped I/O

Interrupts of 8051
5 sources of Interrupts
INT0 and INT1 bars external interrupt inputs
These are processed internally by IE0 and IE1
flags

Two timers which generate int when FFFFH

Serial port interrupt if R1 or T1 is set.

Single step int by software

Interrupt Enable Register :

EA : Global enable/disable.

---

ET2 :Enable Timer 2 interrupt.

ES :Enable Serial port interrupt.
ET1 :Enable Timer 1 interrupt.
EX1 :Enable External 1 interrupt.
ET0 : Enable Timer 0 interrupt.
EX0 : Enable External 0 interrupt.

: Undefined.

Addressing modes
Direct - MOV R0, 89 H, Eg 89 of TMOD
operands 8 bit address field
Internal data RAM and SFRS only

Indirect - ADD A, @ R0
Address is stored in R0 or R1 or SP if 8bits
16 bit addresses only in DPTR

Register Instructions - ADD A, R7

Operands in R0 R7 of selected register bank. Register
bank selected by two bank select bits of PSW

Register specific (Register Implicit) RLA

Immediate Mode ADD A, #100
Indexed Addressing

Addressing Modes
Indexed Addressing
MOVC A, @A+DPTR
JMP @ A + DPTR

Used to access only program memory not data

Used for look up table manipulations
Only PC or data pointer 16 bit storage registers allowed
Base address in PC or DPTR, relative addr in A

Identify the addressing modes

MOV A,#50H
MOV A, R5
MOV DPTR,#nn
MOV 90H, #0a5H
MOV 0A8H, 77H
MOV @R1,#n
MOV A, @R0
MOVX @DPTR,A
MOVC A, @A+PC

 Explain the internal and external program memory as well as data memory of
8051 with the diagram showing their capacities.
Draw the diagram to Interface Program memory of 16K x 8 EPROM to
8051and give its memory map. The address of memory map should start
from 0000H.
Discuss about various addressing modes of 8051.
Explain the interrupt structure. Mention the priority. Explain how least priority
is made as highest priority?
Explain in 8051 instruction set to handle bit addressable RAM.
Draw and discuss the formats and bit definitions of the following SFRs .(a)
IP(b) TMOD(c) TCON(d) SCON
(a) Explain the internal RAM organization of 8051? Discuss how switching
between register banks is possible?
What is the use of SFR? List out the SFR of 8051?
Discuss the advantages of microcontroller based systems over
microprocessor based systems?
(b) With a neat sketch discuss the internal architecture of 8051?
Explain the Flags d program status word of 8051 microcontroller?
Explain the different types of Interrupt in 8051.
Discuss the register set of 8051
Explain the addressing modes of 8051 microcontroller.
Explain the different modes of operation of timer/counter in 8051.
How does 8051 differentiate between the external and Internal prog mem